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Need an expert on vhdl to do a simple task Job:

Id	Projekt/konkurrence	Beskrivelse	Bud/Indlæg	Færdigheder		Påbegyndt		Slutter	Pris (EUR)																					type

Projekt/konkurrence	Beskrivelse	Bud/Indlæg	Færdigheder	Påbegyndt	Slutter	Pris (EUR)
to convert a simple code from matlab to vhdl	I want to convert a code made in matlab to vhdl, to implement it in an FPGA, the code in Matlab is not very long and has 4 small functions.	26	Matlab and Mathematica, Verilog / VHDL	May 21, 2018	May 21, 20185d 22h	€116
implementation of TPC(64,57) decoder	1. Can You make your own version of hardware decoder based on the decoding algorithm. the number of bits however should be remain the same is 64×64,(the decoding methods SISO decoding and Chase Pandiah, type 2 Chase algorithm) and after simulate the decoder on Xilinx ISE and coding in VHDL. 2. and write a brief report explanation how is the hardware structure work and etc.	3	C programmering, Verilog / VHDL, Microcontroller, Elektrisk Ingeniørarbejde, FPGA	May 21, 2018	May 21, 20185d 15h	€30
write an 8-bit CPU in VHDL	I want someone to write in vhdl an 8-bit harvard architecture CPU	6	C programmering, Ingeniørarbejde, Verilog / VHDL, Microcontroller, FPGA	May 17, 2018	May 17, 20182d 5h	€115
stereoscopic vision System using VHDL on FPGA	BId only if u can do only the second Part for $50 and within 3 days stereoscopic vision system the aim stereo vision uses two adjacent cameras to creat a 3d image of the world . A depth map can be created by comparing the offset of the corresponding pixels from the two [login to view URL] for real time stereo vision the image data needs to be processed at a reasonabale frame rate .real-time stere...	2	Elektronik, Verilog / VHDL, FPGA, Image Processing	May 17, 2018	May 17, 20181d 16h	€150
vhdl code for simple parking counter	Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and other at exit of a parking space. When the ultrasonic detects a car, use a counter to count the cars entering and decrement when a car exits. There is an RGB led place at each gate (entry &exit) which is used to indicate opening and closing of gates. Entry gate LED turns green when car detected and space a...	2	Ingeniørarbejde, Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 15, 2018	May 15, 2018Udløbet	€25
process control on fpga(you can either help me in writing code in vhdl or HPS ) OR ANY OTHER POSSIBILTIY	in this project i need just read a analog signal on altera cyclone 5 board and also to realize pt1 element with simple response a(t)=(1-e^-t/T)....it's a simple project and i can explain you in more detail ....so i just want this to signal at the out i.e on gpio pins	10	Elektronik, Verilog / VHDL, Microcontroller, Elektrisk Ingeniørarbejde, FPGA	May 15, 2018	May 15, 2018Udløbet	€26
sending data through cypress WIFI	working with a grideye infrared sensor and looking to send the data through a wifi Cypress connection. We have some experience with this already but i am looking for someone with prior experience with this so that we can work back and forth to get this up and running. I would like to send the data to a be read out with a Visual C sharp interface. Experience with FPGA and VHDL is a bonus	13	C programmering, C++ Programmering, Elektronik, Microcontroller, Verilog / VHDL	May 14, 2018	May 14, 201812d 18h	€1751
VHDL source code for calculator	I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project	16	Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 13, 2018	May 13, 2018Udløbet	€19
VHDL code For FPGA simple calculator	I require a VHDL deisgn code, to construct a simple calculator for two input numbers, testbench and simulation for verification of functionality before using the board.	18	Elektronik, Matlab and Mathematica, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 13, 2018	May 13, 2018Udløbet	€8
FPGA designer using VHDL and/or Verilog for Xilinx and/or Altera FPGA(s)	Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...	12	Elektronik	May 12, 2018	May 12, 2018Udløbet	€103
I want some help with VHDL / FPGA	I need some help with VHDL/FPGAs. I am stuck with some part and would like to fix it asap.	10	Verilog / VHDL, FPGA	May 11, 2018	May 11, 2018Udløbet	€135
Help Implement FPGA calculator, VHDL	I have a Spartan 6 lx9 dev board. I would to connect the board to my computer and perform standard arithmetic calculations and will require help setting up the calculator.	13	Ingeniørarbejde, Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 8, 2018	May 8, 2018Udløbet	€37
fpga soft radio	Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client application to the ADC/DAC. The FPGA is a Xi...	6	Java, Ingeniørarbejde, Elektronik, Verilog / VHDL, Microcontroller	May 8, 2018	May 8, 2018Udløbet	€373
VHDL Multiplexed DDS using iCE40UP5K board. Need post-synthesis Verification and debugging	I'm currently a 4th year degree student undergoing a project to build a Multiplexed DDS using iCE40UP5K breakout board. Apart from the Multiplexed DDS core itself, an i2s module for a DAC chip, Encoder modules for control of waveform parameters and an LCD module are present. Functional verification is done and behavior in simulation is as expected. What is needed is proper post-synthesis ...	6	Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 8, 2018	May 8, 2018Udløbet	-
Help in VHDL and Python	I need some urgent help with VHDL and python for a task which is very important for me!	7	Python, Matlab and Mathematica, Verilog / VHDL, Software Arkitektur, FPGA	May 8, 2018	May 8, 2018Udløbet	€117
Need FPGA VHDL expert and Java expert	Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. I already have a complete project written in vhdl including other modules apart of this project. I need you to simulate and fix the data transmission part between the client application to the DAC AD9764, which is a 14-bit output resolution DAC. FPGA is a Xilinx ...	9	Java, Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, FPGA	May 6, 2018	May 6, 2018Udløbet	€160
Vhdl project	need vhdl to run in board equipment with festive lights........................................................................................................................................................embedded systems project	4	Ingeniørarbejde, Verilog / VHDL, Microcontroller, Elektrisk Ingeniørarbejde, FPGA	May 5, 2018	May 5, 2018Udløbet	€31
Project for Muhammad T. -- 18/05/01 17:20:58	Hi can u help me edit my vhdl code	1	Microcontroller, Indbygget Software, PCB Layout, C++ Programmering, , FPGA	May 1, 2018	May 1, 2018Udløbet	€35
Project for Ahmed Z. -- 18/05/01 17:19:17	Hi can u help me edit my vhdl code	1	Banner Design, Forretningskort, Brochure Design, , Arabisk, Bootstrap	May 1, 2018	May 1, 2018Udløbet	€35
Computer Organisation and Design CPU + VHDL (((Vivado software)) - 30/04/2018 06:00 EDT - 30/04/2018 07:02 EDT	In this project you will create a simple 8‐bit system capable of performing a similar cyphertask. You will be provided with a simple test program to evaluate the operation of your CPU and write report by following the formal_report (TEMPLATE) file in attached.	2	C programmering, Elektronik, Verilog / VHDL, Microcontroller, Montage	Apr 30, 2018	Apr 30, 2018Udløbet	€138

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