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    1,741 need an expert on vhdl to do a simple task jobs fundet, i prisklassen EUR

    I would like to implement a calculator which takes inputs from the ps2 keyboard and displays them on 7 segment.

    €51 (Avg Bid)
    €51 Gns Bud
    5 bud
    Online Tutor Embedded C/C++ 2 dage left
    VERIFICERET

    Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio

    €7 / hr (Avg Bid)
    €7 / hr Gns Bud
    9 bud

    Muktiplexer of 2 to 1 in vhdl using tje software xillinix

    €18 (Avg Bid)
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    3 bud

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    €49 (Avg Bid)
    €49 Gns Bud
    24 bud

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [log ind for at se URL]; a. The source can

    €550 (Avg Bid)
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    3 bud
    find fpga projects Udløbet left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    €406 (Avg Bid)
    €406 Gns Bud
    10 bud

    need report on vhdl of 4 bit alu

    €86 (Avg Bid)
    €86 Gns Bud
    23 bud

    Hi,eveyone.I need a signal processing coding for my work using altra quartus II and VHDL.

    €83 (Avg Bid)
    NDA
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    7 bud

    Implementation of 4 bit alu in VHDL using the software Xillinix ISE I Need report on circuits diagrams, truth table, and simulations results the structure report should go by 1-introduction 2-block diagram 3-Technical Words 4-Implementations 5-Results 6-Conclusion

    €123 (Avg Bid)
    €123 Gns Bud
    6 bud
    FFT working in VHDL Udløbet left

    I want a VHDL code to achieve a N point FFT

    €121 (Avg Bid)
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    16 bud
    Trophy icon Explanation of VHDL code Udløbet left

    I have a VHDL code.. I need someone to explain that code in detail to me.. what stuff it is doing on board..

    €9 (Avg Bid)
    Garanteret
    €9
    0 indlæg

    Hi Ahmed M., Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verified on ILA in Hz. Also comment every line of code.

    €44 / hr (Avg Bid)
    €44 / hr Gns Bud
    1 bud

    Initial Milestone : Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verif on ILA

    €154 (Avg Bid)
    €154 Gns Bud
    1 bud

    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I'm a friend of Alessandro that contact you for a mini project of VHDL

    €50 (Avg Bid)
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    1 bud

    Hello That I want is a basic uart communication with fifo buffer I have a small code ready At last I want a small call for explain

    €49 (Avg Bid)
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    4 bud
    SPI Master Udløbet left

    I want SPI master in VHDL for writing and reading from flash IS25WP032

    €164 (Avg Bid)
    €164 Gns Bud
    15 bud

    I need to generate a code from C++ to VHDL Using GPU.

    €165 (Avg Bid)
    €165 Gns Bud
    7 bud
    VHDL FPGA Project Udløbet left

    ...Project focuses on the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following

    €652 (Avg Bid)
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    6 bud
    Vhdl project Udløbet left

    It is a cluster related vhdl project.

    €249 (Avg Bid)
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    13 bud

    VHDL implemented in altera de2 board

    €295 (Avg Bid)
    €295 Gns Bud
    5 bud

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    €69 (Avg Bid)
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    3 bud

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

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    4 bud
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    Vhdl is needed

    €24 (Avg Bid)
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    6 bud

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    €18 / hr (Avg Bid)
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    3 bud

    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

    €62 (Avg Bid)
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    12 bud

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1073 (Avg Bid)
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    3 bud

    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the

    €12 / hr (Avg Bid)
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    2 bud

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas...

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    1 bud
    VHDL questions Udløbet left

    I have some VHDL questions which I nedd to be solved .

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    Its a small assignment. If you are an expert and have worked on it before. text me

    €113 (Avg Bid)
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    ...work is to see how it would be done from a different point of view. What I would like to be done is: * Check the Simulink model to see if that's done correctly. * Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL i...

    €208 (Avg Bid)
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    9 bud
    PLL in VHDL Udløbet left

    Add in our Design a PLL for variable clock speed

    €152 (Avg Bid)
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    12 bud

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €327 (Avg Bid)
    Fremhævet
    €327 Gns Bud
    3 bud

    VHDL code for "64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction project"

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    Build a VHDL code for 8x8 Wallace multiplier

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    Transfer the design of 32x32 bit combination Multiplier and an 8-bit Word Serial Multiplier( using Cadence simulation ) to Visio block diagram and make sure that signal and port are matched.

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    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

    €19 (Avg Bid)
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    12 bud

    we need an alu of 256*8 memory ..for more information message me

    €28 (Avg Bid)
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    8 bud
    D Class Amp Udløbet left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

    €232 (Avg Bid)
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    11 bud

    I have a Circular iterative CORDIC using Fixed-Point​ Arithmetic. code that I would like to change to Dual Fixed Point code in VHDL/ Vivado

    €35 (Avg Bid)
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    1 bud
    ProjectDone Udløbet left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

    €16 / hr (Avg Bid)
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    11 bud

    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

    €2951 (Avg Bid)
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    11 bud
    Digital To Analoge Udløbet left

    We are a Australian based company in development of Electronics, to run Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation...

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    2 bud

    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    €39 (Avg Bid)
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    4 bud

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

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    9 bud

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    €121 (Avg Bid)
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    7 bud

    Hello i have a code of piano synthesizer using VHDL (vivado) and i want to understand it and fix it ... can you help me ?

    €11 / hr (Avg Bid)
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    1 bud

    ...ASSESSED • Your ability to extract and critically evaluate data for an unfamiliar digital design problem.‎ • The application of appropriate design methods to the VHDL design.‎ • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.‎ • Ability to implement your design solution...

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    7 bud