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    1,681 need an expert on vhdl to do a simple task jobs fundet, i prisklassen EUR

    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

    €116 (Avg Bid)
    €116 Gns Bud
    9 bud

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    €67 (Avg Bid)
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    5 bud

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    €14 / hr (Avg Bid)
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    29 bud

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    €29 (Avg Bid)
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    3 bud

    risc processor design and test, more detail I will provide on chat

    €92 (Avg Bid)
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    16 bud

    Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

    €338 (Avg Bid)
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    9 bud

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €105 (Avg Bid)
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    17 bud

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €358 (Avg Bid)
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    2 bud
    Vhdl LCD finctional Udløbet left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [log ind for at se URL]

    €28 (Avg Bid)
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    5 bud

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    €180 (Avg Bid)
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    12 bud

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    €16 / hr (Avg Bid)
    €16 / hr Gns Bud
    10 bud

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creati...the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    €450 (Avg Bid)
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    10 bud

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attac...

    €96 (Avg Bid)
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    1 bud

    Hello guys I will need these simple tasks for $10 - $15 USD the first until today 8 September the second until tommorow 9 September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would comments on the code and the resulting ima...

    €22 (Avg Bid)
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    2 bud

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    €31 (Avg Bid)
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    2 bud

    Hello guys I will need these simple tasks for $10 - $15 USD until 6 or 7 of September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with n...

    €24 (Avg Bid)
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    3 bud

    I need help with the structural in Xilinx. I will give you full details. Regards

    €21 (Avg Bid)
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    23 bud

    Hello freelancers I have a lot of projects in all engineering fields so i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned

    €33 (Avg Bid)
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    111 bud

    ...name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • ...

    €50 (Avg Bid)
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    1 bud

    Implement an AD2949 IC input block and some more

    €458 (Avg Bid)
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    11 bud

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    €72 (Avg Bid)
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    21 bud
    PRESENT-80 Udløbet left

    ...This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project which can be found in section 3.1 of uploaded pdf (round-based based architecture of PRESENT-80). The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so

    €48 (Avg Bid)
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    4 bud

    ...This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355. The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so that I can perform power analysis on it. Need the...

    €26 (Avg Bid)
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    2 bud

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €337 (Avg Bid)
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    3 bud

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355. The code has already been developed but I'm unable to procure the final result. ( As i can see that the individual modules are successfully executing

    €137 (Avg Bid)
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    9 bud
    need expert on VHDL Udløbet left

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    €63 (Avg Bid)
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    20 bud

    build a communication block in VHDL at Xilinx environment

    €348 (Avg Bid)
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    14 bud

    Implement Communication VHDL Comm port on Xilinx FPGA part

    €109 (Avg Bid)
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    16 bud
    Task in VHDL Udløbet left

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    €99 (Avg Bid)
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    i neeb vhdl project Udløbet left

    i need vhdl project for fpga bord i need skeleton and can move

    €21 (Avg Bid)
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    14 bud

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    €190 (Avg Bid)
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    14 bud

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

    €32 (Avg Bid)
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    6 bud
    vhdl project Udløbet left

    I need you to implement a vcdl design project

    €62 (Avg Bid)
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    16 bud

    ...der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

    €5007 (Avg Bid)
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    3 bud
    Tic Tac Toe in VHDL Udløbet left

    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

    €65 (Avg Bid)
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    4 bud

    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

    €217 (Avg Bid)
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    3 bud

    ...only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be r...

    €317 (Avg Bid)
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    2 bud

    ...my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and time. and this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO

    €50 - €121 / hr
    €50 - €121 / hr
    0 bud
    €14 / hr Gns Bud
    12 bud
    VHDL coding Udløbet left

    HDL coding from block diagram and pseudo algorithm

    €22 (Avg Bid)
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    5 bud

    Develop a musical bell that will play a selected and programmed song in the FPGA.

    €74 (Avg Bid)
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    4 bud

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €114 (Avg Bid)
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    7 bud
    VHDL expert needed Udløbet left

    Expert in VHDL needed to work on a code

    €11 / hr (Avg Bid)
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    14 bud
    Code Conversion Udløbet left

    Small project to write in VHDL

    €96 (Avg Bid)
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    24 bud

    Implement an algorithm in vhdl done in Matlab using System Generator

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    11 bud

    ...έλεγχο του servo πρέπει να παράγουμε μια PWM κυματομορφή. Αυτή η κυματομορφή αποτελ&ep...

    €35 (Avg Bid)
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    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events i...

    €67 (Avg Bid)
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    6 bud

    Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock

    €156 (Avg Bid)
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    1 bud
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    1 bud