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    4,590 fpga freebsd jobs fundet, i prisklassen EUR

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €26 (Avg Bid)
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    6 bud

    Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit...once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.

    €87 (Avg Bid)
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    11 bud

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €138 (Avg Bid)
    €138 Gns Bud
    2 bud

    ...games currently work fine, and one of the two modern flash-based cartridges on the market works correctly, but the other one does not. I believe that both of these carts are FPGA-based, and neither one of them is open-source hardware. I'm looking to hire someone to determine the root cause of the incompatibility, and to propose a circuit design modification

    €1103 (Avg Bid)
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    6 bud
    Looking for Vivado HLS expert 4 dage left
    VERIFICERET

    Need to know the knowledge of Blockchain algorithm and FPGA programming(VHDL/Verilog), C++ programming. Will discuss more via interview.

    €862 (Avg Bid)
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    12 bud

    Hi vlsirajagopal, I need help with FPGA configuration, can we discuss the details?

    €220 (Avg Bid)
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    1 bud

    Hi Rajagopal S., I need help with FPGA configuration, can we discuss the details?

    €220 (Avg Bid)
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    1 bud

    Hi RKY18, I need to help with FPGA configuration, can we discuss details?

    €220 (Avg Bid)
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    1 bud

    Hi ducdctoandh, I am interested in FPGA development, could be discuss the details?

    €221 (Avg Bid)
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    1 bud

    I'd like to invite you to take a look at the job I've posted. Please submit a proposal if you're available and interested. It is about a few hour job. I am using the Deo Nano SoC. I have partitioned the RAM and I can write 32bit words to the partitioned area. I have been fighting with Quartus for a while. I can do everything else on this project. I would provide the c-code so you c...

    €204 (Avg Bid)
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    2 bud

    i need someone teach me how to send and receive data from PCI using c# i have a project need to send and receive data from to FPGA by PCI using c# .net

    €140 (Avg Bid)
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    5 bud

    I require following objectives, methods and methodologies, attached below I require simulation in MATLAB SIMULINK and hardware FPGA

    €266 (Avg Bid)
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    2 bud

    1. picobsd run on Intel VMX/EPT 2. Freebsd 4.1~4.3, picobsd/MFD &crunch diskless run on zip floppy 3. picobsd(router) run elf program with ATM Adapter, target run MUDOS v22pre11 vision 4. BSP,loader kernel setting trace code 5. Diskless use scsi command over internet to another computer

    €13708 (Avg Bid)
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    8 bud

    Please find attached file to read more about the project

    €1926 (Avg Bid)
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    14 bud

    core for a Xilinx FPGA device 32*32 16bit signed integer core on Xilinx Spartan-6 FPGA device, XC6SLX45-CSG324-3

    €95 (Avg Bid)
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    8 bud

    I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.

    €20 (Avg Bid)
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    1 bud

    project include following 1. data received from uart 2. after samples received, data passed to another module for algorithm execution 3. after execution, data send via uart for display 4. parallel receiving and transmission of data while execution of algorithm 5. design block level diagram 6. test bench code in Verilog 7. project should implement on zedboard [log ind for at se URL] code explanatio...

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    5 bud

    Hello I need someone expert in Vivado

    €259 (Avg Bid)
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    9 bud

    ...system verilog language. It should not be more than 250 lines of codes in MIPS and it could be a Maze or Pack Man or another idea depending on the mentor. I will demo this on FPGA that already have these works and files already. here is some description of the task. Every demo must use the VGA monitor as an output device. By default, every demo should

    €279 (Avg Bid)
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    3 bud

    A verilog module shall be generated, that reboots a 7 series FPGA. It shall be compatible with all 7 series FPGAs, but at least with the following: - XC7A200T-2FBG676C - XC7K160T-2FFG676I - XC7K325T-2FFG676I The module will be tested on existing hardware, which uses master SPI x4 boot mode. The module input should be: - clk - up to 160MHz - reboot

    €170 (Avg Bid)
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    3 bud

    An upload of a song is done from computer to Zybo by using a Wifi Pmod and audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth will be done on Zybo. The processed audio will be played using audio codec and necessary options will be displayed on a OLED Pmod for selection.

    €222 - €667
    €222 - €667
    0 bud

    Audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth using wifi PMOD on ZYNQ 7000

    €102 (Avg Bid)
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    2 bud

    I need to add unbound DNS config module to WebMIN in FreeBSD. If you have knowledge about FreeBSD, WebMIN, Perl, its simple task. if not, please don't bid. i wil offer detail info about project after award. Thanks.

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    3 bud

    I have some projects related to embedded I want them to be done one after other... I am looking for a freelancer having good command over different micro controllers and also know how to couple different kind of sensors with different controllerts I need a freelancer who do not think too much about money and less focus on work instead i am looking for someone for whom the work Quality must be supe...

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    Project for Eren K. Udløbet left

    Merhaba, ben Levent. FPGA de Sinyal işleme işleri yaptığınızı belirtmişsiniz. Bu tip işlere ihtiyacımız olabilir. Bize şu ana kadar yaptığınız sinyal işleme / dijital uygulamalarından bahseder misiniz. Saygılarımla

    €889 / hr (Avg Bid)
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    1 bud

    Hi, I have a C++ script which gives me the detections from an SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. Right now, I'm just drawing the bounding boxes around the cars and I'm also counting the detections but I would like to count the cars, not the detections, i.e. a car can

    €248 (Avg Bid)
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    15 bud

    In this project, you will have to design a sequential circuit. The final design will be implemented on an FPGA, therefore, you first have to design an FSM using the hardware description language Verilog.

    €25 (Avg Bid)
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    14 bud

    My Project is object tracking using optical flow on fpga preferably zed board. The application should be able to track a person/ object of interest using optical flow estimation in a HD video. The video is captured through camera n given to the board and the output is obtained through hdmi out of the board which is connected to tv/ computer screen.

    €64 (Avg Bid)
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    1 bud

    The project is to implement object tracking on fpga, preferably Xilinx zed board. The application is to track the object of interest/ person in a HD video. The video captured must be captured from camera and the output given to the hdmi our of the board which can be connected to tv or computer screen

    €90 (Avg Bid)
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    I am fatima zohra , working as intern for a startup company. I need object tracking to be implemented on xilinx zedboard for a HD video. The application should be able to track an object/person of interest from the camera captured video using lucas- kanade optical flow estimation. The output should be obtained through HDMI out which can be connected to computer/ TV screen. Tools like MATLAB , xili...

    €19 - €161
    €19 - €161
    0 bud

    Mitigate the Harmonics distortion by designing Three phase Hybrid power Filter. I want you to do a simulation in Matlab/Simulink. Design 3 phase Hybrid power filter ( ...passive ) to eliminate the harmonic in both source and load current using SRF theory. And when you are done with simulation then I need to implement & test the controller using FPGA.

    €218 (Avg Bid)
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    7 bud

    Bonjour, je souhaiterai me connecter a freeBSD en ssh via une ip local mais je n'y arrive pas. Merci de m'aider.

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    8 bud

    FPGA implementation of FOPID controller using VHDL

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    6 bud

    I need to do Simulation on MATLAB/Simulink. Design 3 phase Hybrid power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current u...power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current using SRF theory. And I need to implement & test the controller using FPGA.

    €162 (Avg Bid)
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    8 bud

    Hi, I am interested in building a very simple demo for a software application I would like to build. The UI is similar to QT Node Editor. I want to make a Python / RTL to FPGA application. Similar to DSP builder for Intel, but different. QT Node editor look and feel. What is your email?

    €9 / hr (Avg Bid)
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    1 bud

    The system will get command through SPI channel to generate custom frequencies (between 0.05hz to 1khz) in 10000 samples for a cycle and save it to a look-up table And in the second command will send the values of the sine-wave to Digital to Analog device

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    12 bud

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant documentation

    €138 (Avg Bid)
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    6 bud

    I am looking for an engineer familiar with STM 32 microcontrollers and FPGA's for interfacing with CCD sensors.

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    I want an MP3 player built on FPGA board based on VHDL language. I want a seasoned hands on FPGAs who can build me this by Apr 2nd, 2019. The FPGA board I have is Xilinx Spartan-6 LX45 (Atlys circuit board) specifically on which it will have to be built and synthesized. I have uploaded an image of the board and feel free to ask me for any information

    €532 (Avg Bid)
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    11 bud

    Schematics checking -Zynq7020 fpga -1GB RAM on PL (For post post process) -1GB RAM on PS -Network PHY RTL8211E-VL -USB PHY USB3320 -Run and Boot OS Via QSPI MT25QL256ABA -SD Card -Check on the power regulator boot up sequence. Suggesting - where and which bank/emio to connect the SFP fiber optic. Prefer no using additional dedicated PHY. SGMII will

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    3 bud

    I need a basic board game, where two players take turns rolling a dice and going around a board similar to monopoly. Once they comple...around the board once, the game ends. The player with the most coin wins. If they land on certain spaces they loose coins and some they gain coins. It has to work on Cyclone V FPGA board using Assembly and C on armv7.

    €102 (Avg Bid)
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    The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The

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    1 bud

    FPGA IMPLEMENTATION of VHDL coding of CONTROL UNIT SYSTEM

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    We want a DDR3 controller for a 7 series FPGA with the following specification: - DDR3 Speed: 533MHz (DDR3-1066) - DDR3 component: MT41K1G8SN-125:A - FPGA: XC7K160T-2FFG676I The controller shall have the following interfaces to the top level: - AXI slave for incoming write data - 32bits width - AXI master for outgoing read data - 32bits width - write

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    ...test bench showing all requirements above can be met. Please only apply for this project if you're 100% sure you're able to do it and have reasonable experience in Verilog & FPGA programming....

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    10 bud

    Hi, I have a C++ script which takes the frames from a SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. I have added some counters to count the numbers of elements detected (vehicles and pedestrians). It counts a lot of elements because it counts in every detection. I would like

    €213 (Avg Bid)
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    26 bud

    Need an implementation of a TDC on the Artix-7 for a LIDAR application. Should work on Digilent Cmod-7 Board for hardware testing. Higher pay for higher resolution. Inports: clk (144MHz) rst (active low) startstop (after reset, first rising edge is start signal, second rising edge is stop signal) Outports: data ready (active high) dataout (16bits) Should reset every time a reading is needed, a...

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    ...of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard. Important note, your implementation should ONLY use PL part of the fpga and no FPGA specific units (like cpu cores, AXI bus, HARD

    €277 (Avg Bid)
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    4 bud

    Hi totori1990,I found that you applied for the project of developing fpga application on Solarflare AOE SFA7942Q device which is titled as "Freelance FPGA engineer". I'm considering a similar project. If you took that project, I want to ask you more details about the result.

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    1 bud