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    2,672 read data adc fpga jobs fundet, i prisklassen EUR
    pcb desigg Udløbet left

    timer concept lcd 3 relay 3 buttons rtc 6 adc (op amp circuit)

    €93 (Avg Bid)
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    19 bud
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    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    5 bud

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    €125 (Avg Bid)
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    5 bud

    ...given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comparing MATLAB result with Xilinx@ System Generator result for above specified 3 images with different

    €123 (Avg Bid)
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    1 bud

    VHDL implemented in altera de2 board

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    4 bud

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

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    2 bud

    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

    €2146 (Avg Bid)
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    16 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    5 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €157 (Avg Bid)
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    7 bud

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    €304 (Avg Bid)
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    5 bud

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of a...

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    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

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    3 bud

    Need help program FPGA with Artix-7 using Verliog.

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    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

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    21 bud

    Necesito obtener mediciones de un PIN de la tarjeta y mostrarlos en la PC usando DMA.

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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    1 bud

    Implement the Zen Protocol in the FPGA and update the Mining App

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    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

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    15 bud
    FPGA Designing Udløbet left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

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    14 bud

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

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    Its a small assignment. If you are an expert and have worked on it before. text me

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    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

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    build a matlab simulation of pmu without time stamping for 1 phase use recursive algorithm for [log ind for at se URL] each sub system like adc etc

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    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

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    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the play...demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

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    Fremhævet
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    1. Design platform: VIVADO 18.2 2...xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 ...

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    Use the following components to build a small SMPTE Timecode reader / generator: Functions: 1) Read LTC input through 3.5mm Audio jack. 2) Output LTC via 3.5mm Audio jack (Use the same port for bi-directional). 3) Retain the synched Timecode with an RTC without slippage. 4) Display the Timecode constantly on the OLED display. 5) Sync Between two Similar

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    1. Design platform: VIVADO 18.2 2...xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 ...

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    6 bud

    ...basic basic. The firmware needs to initialize GPIO, ADC and Timers. Then in a main while(1) loop, capture 7 analog values from the ADC (running in DMA mode) and apply a user value to the two Timer PWM outputs. Use the attached STM32 cube configuration file for details on which pins are GPIO/Timer or ADC. Only bid for the job is you have experience with

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    3 bud

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

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    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

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    ...peripherals. Has functions to read/write I2C data to/from the IR Thermometer, Heart Rate & Pulse, Accelerometer, Gyro, Compass, ECG Clock, and Battery Charger. Has functions to read/write 4-wire SPI to/from the ECG sensor Has functions to read I2S data from MEMS microphone Has functions to read ADC value for Glucose Monitor ...

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    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

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    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [log ind for at se URL] I want video to

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    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

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    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

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    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

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    ...myself, I need help in writing and the circuit diagram and the code, the code to use can be python or C programming or Embedded system using the LED, solar panel, Amplifiers, ADC, MUCs Objectives Objective 1- Develop a prototype of the VLC and showcase the effectiveness by using LEDs.‎ Objective 2- To presents the comprehensive experimental work on

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    D Class Amp Udløbet left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    ProjectDone Udløbet left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

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    build a phasor calculator in simulink to display voltage current and [log ind for at se URL] should have input filter,ADC block,DFT,sequence analyzer and display voltage current pf lag or lead

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    4 bud
    abiramiamanm Udløbet left

    vlsi coding using QUARTUS II software FPGA

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    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

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    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

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    Digital To Analoge Udløbet left

    ...company in development of Electronics, to run Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation

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