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    2,563 read data adc fpga jobs fundet, i prisklassen EUR

    timer concept lcd 3 relay 3 buttons rtc 6 adc (op amp circuit)

    €91 (Avg Bid)
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    19 bud

    Needs to hire 2 Freelancers We are looking for designer to design Video object tracking : 1- CPU, CUDA based or FPGA accelerated algorithm . 2- Multi-target Detection/ tracking . 3- Moving object detection . 4- High accuracy , auto scaling , occlusion recovering . 5- fixed camera or moving camera. 6- Image Stabilization . 7- Move on Move tracking

    €1103 (Avg Bid)
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    5 bud

    ...STM32F4Cube HAL library and STM32CubeMX configurator. Target STM32F407VE MCU. Peripherals used: USB OTG FS port, Waveform DAC output pin, waveform ADC input pin to input waveform for measuring and 4 ADC input pins for parameters settings from pots. Generator : 0 - 3.3V Amplitude both square and sawtooth waveforms positive in relation to GND . No offset

    €2243 (Avg Bid)
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    13 bud

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    €391 (Avg Bid)
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    4 bud

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    €222 (Avg Bid)
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    2 bud

    We are looking for someone with engineering background, preferably knowledge in FPGA related stuff to translate some tehnical documents. Google translate is not acceptable.

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    27 bud

    Looking for a mentor in advanced FPGA development using Altera Max 10 FPGA board specifically.

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    9 bud

    1. Identify a good value and properly sized CPLD/FPGA and toolset (toolset needs to be relatively easy to configure) to accommodate the required functionality. 2. Develop the CPLD/FPGA code. The device needs to take as inputs a set of states (from a microcontroller so either as an I2C command or as a 3 digital input code, along with 3 digital inputs

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    i want atmega8a programmer for adc and timer programming . please if any one contact me

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    I need a network of thermostats that send data over Power Line Communication to a router where it is then sent over Ethernet and stored on a server. I will need to have software to access and display the data in graph form. There are other components that I need that are not so detailed. I need consulting for the design and components to use for both

    €123 (Avg Bid)
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    PCB design 4 hours left

    ...square or rectangular with maximum dimensions of 9.5 cm x 9.5 cm. The PCB should hold 5 of the following boards: [login to view URL] There should be some minimal interconnection between the 5 boards (more details to be provided). The USB ports on each of the boards will be used only for programming

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    ...infinite scroll since a few year, but since today we have switched to SSL, now the infinite scroll raise an error because of SSL to see the error open [login to view URL] then and scroll down, you will see it is not loading the next pages Note : It is not possible to change the HTML code on the server but i can

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    I have a unusual ADC/DAC/GPIO hybrid device connected to a Microcontroller via SPI. I need a driver for the ADC & DAC as well as digital IO from the device

    €454 (Avg Bid)
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    36 bud

    Development of an embedded C driver for an ADC/DAC IC connected via SPI

    €338 (Avg Bid)
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    26 bud

    I am looking for Xilinx SDx OpenCL expert, who can convert github miner project into FPGA hex file in Xilinx SDx. Don't bid if you do not have experience.

    €4273 (Avg Bid)
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    Reading of sensor via PMOD on FPGA Xillinx. More details via messenger Freelancer.com with full requirements.

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    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €132 (Avg Bid)
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    7 bud

    ...for 1 hour work max! We have the attached 128*128 image, i just need some fixes and to run it and produce the new image after the median filter we pass it through microblaze FPGA in the c program. I specifucally want: 1. instead of arrays i want the resulting image to come off like a txt if possible 2. i want inside the code to include the part we

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    Hello everybody, I want a simple median filter in c embedded through a micriblaze fFPGA. I have some part of the code ready. i need it in 1 hour. If you got it lets talk :)

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    High frequency electronics: signal, sensors and electronic interface to ADC

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    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

    €9 (Avg Bid)
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    1 bud

    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

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    Hello Dear, I have an urgent quick project. I have a...quick project. I have an embedded median filter of a table image 128*128 in c. I have the c code ready already. I just need you to take the median image 8*8 a nd pass it through FPGA with and without cache memory and then deliver the new images we get. It is for today please reply if interested

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    1 bud

    Hello Freelancers, I would like to pass my table image through a FPGA microblaze (both with cache and without cache) and have a s deliverables the 2 new images we get as results. This is for TODAY. Thank you in advance :)

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    ...need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files

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    ...need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files

    €95 (Avg Bid)
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    1 bud

    ...USD the first until today 8 September the second until tommorow 9 September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass

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    3 bud

    Antivirus servers, ADC server , DC Server, Active Directory, IIS , Networking . Voice Server , Cent OS configuration's.

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    19 bud

    ...320x240-optional-touch-screen WIth 1 button: On/Off and a switch : Flash ESP32. The ESP32-WROOM-32D has to be also in charge of measuring the remaining battery using the ADC. If you think you can do it, start the bidding proposal with "ESP32TFT". If you need more info or pictures of the existing (but discontinued hardware), do not hesitate to contact

    €1007 (Avg Bid)
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    ...1. STM32F103 Programmer A.) Experience on CubeMX, Truestudio for code generation. B.) Strong hands on CAN, SPI, USART, 1-Wire, I2C, USB Protocols. C.) Ability to works with ADC, GPIO(IN, OUT) and WDT. D.) Prior programming experience in Automotive Domain. E.) Ability to power optimization through programming(sleep mode, LP Mode) for battery operated

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    ...sensor (heartbeat) with ADC (ADS1015) I used the example provided below, however I wasn’t able to get the correct bpm. Problem is shown as attached(can be found in comments of website) [login to view URL] 2) temperature sensor (mcp9808) Yet to begin 3) GSR sensor (probably also with ADC (ADS1025)) Yet to begin

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    ...will need these simple tasks for $10 - $15 USD until 6 or 7 of September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table

    €24 (Avg Bid)
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    3 bud

    I had experience in UART I2C ADC PWM TIMERS AND COUNTERS. I had experience in automotive domain. Now I am a Embedded software Engineer.

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    ...fields so i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers

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    ... I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the clock frequency is correct. Can you please help me , i need go deliver the project asap :).

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    ...USB_OTG Required interfaces: USB OTG, UART, SPI, I2C , 1-wire, Timers: experience with all modes available in STM32F4 are required, Interrupts and DMA experience is required, ADC conversion into a buffer using ISR interrupts triggered by a timer. ------------------------------------------------------------------------------------------------- This particular

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    Implement an AD2949 IC input block and some more

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    ... About 35 main modifications. Example: “Add three analog inputs circuits with voltage dividers 5V to 3.3V and call them “XXP1” and “XXP2” and “GPS”. Hook them up to adequat ADC pins on Teensy. Copy protective circuit from “X POSITION SENSOR” to these.” “Add power indicator LED on “+12V XCU” rail.” “...

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    The firmware will do a few different things. sometimes it will be scanning the input from the PD and sometimes it will be activating the LED. it is the most import to input...will do a few different things. sometimes it will be scanning the input from the PD and sometimes it will be activating the LED. it is the most import to input PD signal and ADC.

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    looking for someone who can convert Open CL algorithm into FPGA Verilog project

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    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

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    we want to establish the data link between remote data station and our server via VHF Meteor Brust transceiver. as remote sites is about 150km far from main station/server. the site is full of terrains and there is no other way of communication. (satellite is very costly and GSM signal are not available on remote site. x.25. Electronics Radio Circuits

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    I have a double layered PCB ( top and Bottom, no more layers )with mainly 1 ARM Microcontroller, one 24bit ADC and a communication chip on there. I need you to build the autodes eagle schematic file for me. I can not provide the pcb itself but detailed photos in high resolutions of both sides. I will deliver a sample photo upon request.

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    ...Testing Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer

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    ...• Experience with a task tracking systems, task estimations and time tracking. • Understanding digital electronics and ability to read schematics, analog electronics is a big plus but not obligatory • Experience with FPGA is an asset • Understanding blue prints, engineering drawings and familiarity with PCBs • Experience with measurement instruments

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    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    ...Software Programmer for ECU Project, Whose having strong knowledge on 32 bit controller programming with automotive experience. Protocols: SPI, CAN (Must) Device drivers: ADC , DAC, PWM Should have good understanding about electronics hardware. Duration of the project: 45 Days to 60 Days Deliverable : Complete BSP + Sample App RTOS Integration

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    26 bud

    ...consulting and code-writing for my FPGA board: [login to view URL] I have 6 PDM mics I got from Adafruit: [login to view URL] I want to do synchronized-recording of the audio from the mics into FPGA-board, and stream this recording to

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    program with fpga to control TCP data and flow.

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    21 bud