Verilog / VHDL Jobs og konkurrencer

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Projekt/konkurrence Beskrivelse Bud/Indlæg Færdigheder Påbegyndt Slutter Pris (EUR)
networking simulation it is assumed i have wifi access point and lifi access point as a start of the network data rate of both access point AP start from 0 then we have user1 is connected to lifi AP we have a condition of handover , the user is connecting to wifi AP in case of disconnect from the lifi AP for a while then user connect back to lifi this cause changing in data rate of the APs if you can do this job then i... 8 Matlab and Mathematica, Verilog / VHDL, Software Arkitektur, Software Udvikling, FPGA Sep 24, 2017 I dag6d 9h €118
Expert in LISP AND MATLAB needed expert in LISP and Matlab to convert a code 6 Matlab and Mathematica, Verilog / VHDL, Elektrisk Ingeniørarbejde, Prolog, Lisp Sep 24, 2017 I dag6d 2h €27
hire a matlab expert details will be given in the chat 24 PHP, Matlab and Mathematica, Verilog / VHDL, Algoritme, Software Udvikling Sep 23, 2017 Sep 23, 20175d 1h €16
MIPS Code to C++ Translation I need to convert mips code to C++. File Size is only 5K. My MAX Budget is 500 USD. I think it will take 3 days or less. I will discuss in detail over the chat. 24 Verilog / VHDL, Prolog, C++ Programmering Sep 22, 2017 Sep 22, 20174d 19h €455
Need matlab expert needed -- 2 small project one hour project. please bid if you have experienced. 5 PHP, Matlab and Mathematica, Verilog / VHDL, Algoritme, Maskinoplæring Sep 22, 2017 Sep 22, 20174d 8h €4
Need matlab expert needed small project one hour project. please bid if you have experienced. 8 PHP, Matlab and Mathematica, Verilog / VHDL, Algoritme, Maskinoplæring Sep 22, 2017 Sep 22, 20174d 8h €4
PHP, Verilog / VHDL, Metahandel, Fortran, Lua Sep 21, 2017 Sep 21, 20173d 13h
NEURAL NETWORK BASED FACE RECOGNITION The project requests to design a system to recognize different faces. Face acknowledgement is a pattern recognition problem, so comparison between the faces will be done with the help of one neural network. 8 Verilog / VHDL, CUDA, Maskinoplæring, Ansigts Genkendelse, FPGA Sep 21, 2017 Sep 21, 20173d 5h €81
Verification of Motion Estimator using Universal Verification Methodology (UVM) Motion Estimation is a process to determine the motion vectors that describe transformation one 2D image to another; usually from adjacent frames in the video sequence. To obtain motion estimation block matching algorithm is used. Usually, the only difference between much of content in subsequent frames is motion. The task is to detect blocks of video data from successive frames that are related o... 4 Verilog / VHDL Sep 20, 2017 Sep 20, 20172d 15h €183
JPEG2000 image compression in matlab JPEG2000 in matlab, image processing 15 Matlab and Mathematica, Verilog / VHDL, Algoritme, LabVIEW, FPGA Sep 20, 2017 Sep 20, 20172d 4h €28
matlab image compression image compression using JPEG2000 in matlab 13 Matlab and Mathematica, Verilog / VHDL, Algoritme, LabVIEW, FPGA Sep 20, 2017 Sep 20, 20172d 4h €32
FPGA implementation of a data structure We have decided to move a part of our software to FPGA to achieve lower latency. The incoming data (that will be provided to you) will update RAM in the FPGA . More info is available with a quick chat. 16 Verilog / VHDL Sep 20, 2017 Sep 20, 20171d 21h €395
Real time 2-Dimensional FFT on FPGA using Verilog HDL Please I wanna find some who can help me to finish this project as soon as possible, someone who is really expert with FPGA, Verilog HDL and Vivado. 20 Elektronik, Verilog / VHDL, Digital Design, FPGA, Programming Sep 14, 2017 Sep 14, 2017Udløbet €76
i want to amibroker afl my own condition plz contact and help me 7004926136 dear sir i am shiv shankar pandit from ludhiana i have requeird my stratgy use in afl formula two zig-zig 1.----zig zag parameeter 0.1 to 5 2. ---position ----- both / only buy / only short / ALL Breakout 3. ---buy = first swing high breakout condition aply -- trade .01 point to 500 point after/ befor and if zig -zag 1 is up then i will take position sell on zig-zag low break... 2 Visual Basic, Verilog / VHDL, Metahandel, Fortran Sep 14, 2017 Sep 14, 2017Udløbet €58
Business card + screen wallpaper + painting - open to bidding Dear all, we are hiring for a designer to design our : 1. business cards -> modern, simple, clear, clean 2. screen wallpaper painting to be used on our laptops and printed and hanged on our office walls -> with our logo and our core values: Excellence, Reliability, Efficiency Looking forward to your feedbacks. Logo attached here. Good luck 29 Verilog / VHDL, Algoritme, Teknisk Forfatning, Virtuel Assistent, PDF Sep 14, 2017 Sep 14, 2017Udløbet €84
FPGA implementation of viola jones face detection algorithm for multiple face detection I need to implement a system which consists of display, OV7670 camera and zedboard(FPGA board) and should ble to detect multiple faces in input imsge. 4 Verilog / VHDL, Algoritme, Image Processing Sep 9, 2017 Sep 9, 2017Udløbet €1619
Transistor modelling Project objectives : This research includes the development of the strong, robust transistor model which will best suitable for the microwave amplifier application. This model can be used to get some linear and nonlinear measurements, which consists of design, development and circuit analysis of HEMT based FET model and also states the experimental result of existing models. Using AWR microwa... 0 Verilog / VHDL, Very-large-scale integration (VLSI) Sep 8, 2017 Sep 8, 2017Udløbet -
Design a 8-bit VHDL code design 22 Verilog / VHDL Sep 6, 2017 Sep 6, 2017Udløbet €20
Design a 8-bit MPZ using HDL description The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input. An n-bit MPZ unit finds r (1 ≤ r ≤ n) matches in exactly r cycles. Design an 8-bitMPZ using HDL description. You may use ModelSim or Quartus II software. In your implementation, you may have a mix of behavioral and structural descriptions for modules/components. Slight modifications of t... 8 Verilog / VHDL Sep 6, 2017 Sep 6, 2017Udløbet €31
ns2 project Develop and compare 2 methods. [url fjernet, log ind for visning] trust value of each node by using watchdog method [url fjernet, log ind for visning] contains different formula for trust calculation 3 Verilog / VHDL Sep 4, 2017 Sep 4, 2017Udløbet €217
Real-time pulse compression radar waveform generation and digital matched filtering I have added IEEE paper below. I need following three requirements. 1. project explanation. what is the plan to implement the paper. 2. Implement the paper in matlab. Need matlab simulations 3. Write a verilog code for the paper. Results has to match with matlab simulations. 7 Matlab and Mathematica, Verilog / VHDL Aug 29, 2017 Aug 29, 2017Udløbet €170
networking ns2 ns2 15 Verilog / VHDL, Cloud Computing, CUDA, FPGA Aug 28, 2017 Aug 28, 2017Udløbet €533
Elektrisk Ingeniørarbejde, Elektronik, Ingeniørarbejde, FPGA, Verilog / VHDL Aug 27, 2017 Aug 27, 2017Udløbet
Token Bucket in VHDL Details in chat, contact me for more if interested. 9 Verilog / VHDL Aug 22, 2017 Aug 22, 2017Udløbet €21
light to light conversion Pv fed led lighting system: Harmony search algorithm based controller design I am using altium nano board . i need verilog code for above algorithm. 5 Verilog / VHDL Aug 17, 2017 Aug 17, 2017Udløbet €123
Project for izafeirakis Hi izafeirakis, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 5 Verilog / VHDL, Teknisk Forfatning, PDF, Word, , Montage Aug 16, 2017 Aug 16, 2017Udløbet €69
Project for fattouma92 Hi fattouma92, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 1 Elektronik, Verilog / VHDL, , FPGA Aug 16, 2017 Aug 16, 2017Udløbet €65
VHDL expert programmer and Mathematician -- 3 I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms and matlab 19 Matlab and Mathematica, Verilog / VHDL, Algoritme, FPGA Aug 16, 2017 Aug 16, 2017Udløbet €109
Modify Altera FGPA Project and corresponding c library We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we nee... 16 C programmering, Verilog / VHDL, FPGA Aug 8, 2017 Aug 8, 2017Udløbet €1003
Make ASIC or FPGA chips optimized for an OpenCL application We would need design and production of FPGA or ASIC units optimized to run just a specific OpenCL program as fast as possible. This OpenCL program calculates cryptographic hash functions and has a benchmark report that displays how many hash calculations are made per second. Your FPGA/ASIC should calculate at least 20 billion hashes per second while executing our OpenCL kernel, and should con... 6 Elektronik, Verilog / VHDL, Microcontroller, OpenCL, FPGA Aug 8, 2017 Aug 8, 2017Udløbet €4535
Implementation of generalised spatial modulation in visible light communication i need expertise in wirless communication domain people 4 Verilog / VHDL, Microcontroller, Kommunikation, FPGA Aug 5, 2017 Aug 5, 2017Udløbet €121
VHDL code to measure the voltage and print it in HIX in the digital numbers - open to bidding it has to print it in HIX in the digital numbers of the bored max voltage is 3.3 should be print as 3FF because we r working in 10 bits 6 Elektronik, Verilog / VHDL, Elektrisk Ingeniørarbejde, Digital Design, Kredsløbs Design Jul 28, 2017 Jul 28, 2017Udløbet €101
VHDL expert programmer and Mathematician -- 2 I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms 14 Matlab and Mathematica, Verilog / VHDL, Algoritme, FPGA Jul 25, 2017 Jul 25, 2017Udløbet €296
Project for han121kun Hi han121kun, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 2 Verilog / VHDL, PCB Layout, Produkt Design, , Software Udvikling, Programming Jul 25, 2017 Jul 25, 2017Udløbet €141
Design block in VHDL Mirror unit receives data stream via Avalon ST interface which is buffered and processed if necessary. Each steam starts with Control packet which contains description about the image like interlacing, width and height or definition of the data received (Altera's VIP has it's own protocol, it is assumed that you familiar with it). Please read attached document for more detailed descr... 4 Verilog / VHDL Jul 23, 2017 Jul 23, 2017Udløbet €442
I would like to hire an Assembly Developer Convert this c++ code to marie #include <iostream> using namespace std; int square (int a); void main() { int x; for (int i=10; i<100;i++) { x = square(i)%100; if (x==i) cout<<x<<endl; } } int square(int a) { return (a*a); } 10 Verilog / VHDL, Software Arkitektur, Montage, Software Udvikling Jul 20, 2017 Jul 20, 2017Udløbet €62
Simulations Converting PDF 2D designs to to Simulation Revits. Clients budget is below: $20,000 milestoned in 18 Stages: $1,100 per stage Structural/ Animation Data Conversion Formats: w/ Lumion 7, Autodesk,SolidWorks and Lumion • Lumion 7 is fully compatible with Revit, Sketchup. ... 3D Model import: DWG, DXF, DAE, FBX, MAX, 3DS, OBJ, SKP. ... Image import: TGA, DDS, PSD, JPG, BMP, HDR, PNG. Or... 33 Verilog / VHDL, 3D Rendering, Solidworks, 3D Modellering, Autodesk Revit Jul 20, 2017 Jul 20, 2017Udløbet €13420
Project for microembedded Hi microembedded, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 8 Trådløs, Ingeniørarbejde, Elektronik, Matlab and Mathematica, Verilog / VHDL, Jul 18, 2017 Jul 18, 2017Udløbet €22
FPGA VHDL for DDC/DUC and MODEM I am looking for developer for digital signal Processing , I need VHDL code for : 1- Digital Up converter . 2- Digital Down Converter . 3- SSB , LSB , USB , ISB Modulation / demodulation . 4- AME Modulation/ demodulation 5- FM Modulation/ demodulation . 6- FSK Modulation/ demodulation 7- GMSK Modulation/ demodulation 8- QAM Modulation/ demodulation 9- JESD204 . 10- AES256 . 12 Matlab and Mathematica, Verilog / VHDL, Algoritme, FPGA Jul 18, 2017 Jul 18, 2017Udløbet €2229
Project for alexkokh87 Hi alexkokh87, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 8 Oversættelse, Elektronik, Verilog / VHDL, C++ Programmering, , Arduino Jul 18, 2017 Jul 18, 2017Udløbet €175
Project for adityalim Hi adityalim, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 7 Oversættelse, Korrektur Læsning, Verilog / VHDL, Powerpoint, CV, Jul 18, 2017 Jul 18, 2017Udløbet €179
Project for mardelmariam Hi mardelmariam, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 Verilog / VHDL, Videnskabelig Forskning, PCB Layout, Produkt Management, , Fysik Jul 18, 2017 Jul 18, 2017Udløbet €179
Project for intuido Hi intuido, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 5 C programmering, Verilog / VHDL, Microcontroller, Elektrisk Ingeniørarbejde, , Digital Design Jul 18, 2017 Jul 18, 2017Udløbet €179
Project for hzarsuela Hi hzarsuela, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 4 Elektronik, Matlab and Mathematica, Verilog / VHDL, Videnskabelig Forskning, Microcontroller, Jul 18, 2017 Jul 18, 2017Udløbet €171
генератор gps кода Local GPS code generator. Must provide GPC C/A code for any GPS satellites (selectable by parallel code) and programmable delay (appointed by 16bit parallel code). Time resolution 20ns. По русски: генератор gps кода с задаваемой задержкой, номером спутника и разрешением 20 ns Во вложении мои наработки. 3 Verilog / VHDL, GPS, FPGA Jul 16, 2017 Jul 16, 2017Udløbet €245
Verilog question I need help in a verilog question. I am a beginner in verilog so need some help. 16 Verilog / VHDL Jul 16, 2017 Jul 16, 2017Udløbet €16
Project for andriysu1960 Hi andriysu1960, I noticed your profile and would like to offer you my project. We can discuss any details over chat. 2 Verilog / VHDL, Microcontroller, , Kredsløbs Design, FPGA Jul 15, 2017 Jul 15, 2017Udløbet €8
Small Verilog code I need a small verilog code as soon as possible. 28 Verilog / VHDL, Digital Design, FPGA Jul 15, 2017 Jul 15, 2017Udløbet €228
wishbone bus and can bus bridge - open to bidding making a bridge IC between wishbone bus and can bus that will take data from wishbone bus and put it on can bus and vice versa 5 Ingeniørarbejde, Elektronik, Verilog / VHDL, Microcontroller, Elektrisk Ingeniørarbejde Jul 14, 2017 Jul 14, 2017Udløbet €261
Asic Design / FPGA I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software Contact me for more details 16 Verilog / VHDL, FPGA Jul 12, 2017 Jul 12, 2017Udløbet €117
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