Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Ansæt Verilog / VHDL Designers

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    17 jobs fundet, i prisklassen EUR
    FPGA, VDHL coding 6 dage left
    VERIFICERET

    Please contact me if you expert In FPGA, VDHL coding

    €157 (Avg Bid)
    €157 Gns Bud
    4 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €81 (Avg Bid)
    €81 Gns Bud
    4 bud

    The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

    €176 (Avg Bid)
    €176 Gns Bud
    28 bud
    €23 Gns Bud
    4 bud

    Verilog simulation of two action-reaction processes

    €36 (Avg Bid)
    €36 Gns Bud
    3 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €135 (Avg Bid)
    €135 Gns Bud
    7 bud

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    €188 (Avg Bid)
    €188 Gns Bud
    6 bud

    Vhdl is needed

    €23 (Avg Bid)
    €23 Gns Bud
    5 bud

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €443 (Avg Bid)
    €443 Gns Bud
    13 bud
    Diseño FPGAs en VHDL 2 dage left
    VERIFICERET

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas.

    €29 (Avg Bid)
    €29 Gns Bud
    1 bud

    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

    €21 (Avg Bid)
    €21 Gns Bud
    5 bud
    VHDL questions 1 dag left

    I have some VHDL questions which I nedd to be solved .

    €16 (Avg Bid)
    €16 Gns Bud
    6 bud
    Trophy icon VHDL Design 1 dag left

    Concurso enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. El concurso comienza hoy y termina en 7 días. Los participantes tienen una semana para avanzar todo lo que puedan. El participante ganador dispondrá de 10 días más para finalizar ...

    €30 (Avg Bid)
    €30
    1 indlæg
    FPGA Designing 1 dag left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    €47 (Avg Bid)
    €47 Gns Bud
    15 bud

    build a matlab simulation of pmu without time stamping for 1 phase use recursive algorithm for [log ind for at se URL] each sub system like adc etc

    €43 (Avg Bid)
    €43 Gns Bud
    6 bud

    My aim of this work is to see how it would be done from a different point of view. What I would like to be done is: * Check the Simulink model to see if that's done correctly. * Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL in the simplest possible way. I...

    €208 (Avg Bid)
    €208 Gns Bud
    9 bud
    PLL in VHDL 6 timer left
    VERIFICERET

    Add in our Design a PLL for variable clock speed

    €152 (Avg Bid)
    €152 Gns Bud
    12 bud