Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Ansæt Verilog / VHDL Designers

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    15 jobs fundet, i prisklassen EUR

    i want long term employee. if you have quartus software, please bid here

    €7 / hr (Avg Bid)
    €7 / hr Gns Bud
    6 bud

    I need some one write veriloge code for pan tompkins algorithm to detect ECG QRS, Bpm , Heart rate , contact ECG sensor with FPGA zybo

    €17 (Avg Bid)
    €17 Gns Bud
    1 bud

    SystemVerilog/ UVM / Testing DUT Simulation Rtl integration/design verification of IP

    €9 / hr (Avg Bid)
    €9 / hr Gns Bud
    2 bud

    I need some one write veriloge code for pan tompkins algorithm to detect ECG QRS, Bpm , Heart rate

    €26 (Avg Bid)
    €26 Gns Bud
    3 bud

    Have some code which needs updating.

    €87 (Avg Bid)
    €87 Gns Bud
    6 bud

    Need some one who have experience in development for vibration monitoring application along with FFT from scratch.

    €2330 (Avg Bid)
    €2330 Gns Bud
    7 bud

    I have a verilog model for digital data and clock recovery using DLL, the code needs debugging, so it needs someone who has a good background in this domain!

    €22 (Avg Bid)
    €22 Gns Bud
    3 bud

    I have working verilog modules, need to convert to system verilog module and add UVM for test bench

    €122 (Avg Bid)
    €122 Gns Bud
    4 bud
    Verilog HDL 2 dage left

    building a simple hardware description of a sequential circuit in Verilog HDL which goal is to produce clock signals for serial communication baud rate generators.

    €72 (Avg Bid)
    €72 Gns Bud
    15 bud

    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

    €248 (Avg Bid)
    €248 Gns Bud
    5 bud

    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

    €139 (Avg Bid)
    €139 Gns Bud
    5 bud

    [log ind for at se URL] and research paper Explanation [log ind for at se URL] and PPT

    €122 (Avg Bid)
    €122 Gns Bud
    2 bud

    I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [log ind for at se URL] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for bcu and 650 for cvp I pay you 250 € after successful test From my experience guys are taking a pc miner version that e...

    €176 (Avg Bid)
    €176 Gns Bud
    3 bud

    I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project

    €15 (Avg Bid)
    €15 Gns Bud
    5 bud

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    €147 (Avg Bid)
    €147 Gns Bud
    3 bud