Developing Verilog-AMS Mixed signal functional model design

2+ years experience in developing Mixed Signal Functional Model Design.\r\n\r\nTechnical Skills\r\nVLSI Tools Cadence Tools(NCVerilog, NCSim, Simvision, NCelab, Virtuso Schematic Editor, Mixed Signal Environment)\r\nMentor Graphics Tool Suite(ModelSim).\r\nEditor Tools(nEdit, vim).\r\nXilinx tool for FPGA(ISE).\\r\\no Design Sync tool.\r\nHDL Languages: Verilog-D, Verilog-A, Verilog-AMS(WREAL).\r\nOther Languages: PERL, SHELL, PASCAL.\r\n\r\[login to view URL] Signal Functional Model Design for PLL: Designing mixed signal functional models (WREAL) for PLL IPs such as VCO, PFD, LPF, Charge Pump, Frequency divider.\\r\\nResponsibilities: Understanding and implementing the Design in RVM(WREAL) .Quality and reliability Check. Random testability. Module level integration.\r\n\r\[login to view URL] Signal Functional Model Design: Designing mixed signal functional models (WREAL) for various IPs such as DC-DC converters, Reference generators, XTAL oscillators, Supply voltage supervisor, Flash LDO and VCC detect IPs. \r\nResponsibilities: Understanding and implementing the Design in RVM(WREAL) and Verilog-A. Power aware and non power aware design strategy. Quality and reliability Check. Random testability. Module level integration.\r\n\r\[login to view URL] Behavioral Model Design: Developing digital functional models for various IPs like GPIOs, Precision oscillator, SAR ADC, Band-Gap, POR models.\r\nResponsibilities: Understanding and implementing the Design in Verilog-D. Power aware and non power aware design strategy. Quality and reliability Check. Random testability. Top level integration.\r\n\r\[login to view URL] Signal Behavioral Model design for Tester-on-Chip: Developing mixed signal functional model for Pin-Electronics block for Tester-on-Chip project. The aim of this project was to develop a single chip functional tester which has the ability to perform functional testing. Pin-Electronics block has a capability to force patterns from the driver, retrieve the data from the Device Under Test (DUT) and process to perform the functional testing.