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I have a logisim design and Verilog code that want to be converted to VLSI layout 1- Implement the design using Magic VLSI layout tool to generate the layout [login to view URL] 2- Test the design using irsim to simulate the project. [login to view URL] if you are intrested and for futher more information let me know - Stick diagram for each component of your design. The build blocks components are enough. -Testing strategy and results: they should show instructions to simulate and verify your design, by including Linux terminal commands for Magic and Irsim used to run your project with few different inputs.