Need someone good expert in computer architecture -- 3

Need someone good expert in computer architecture In this project, you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch resolution in D. Non-memory hazard detection in D. a) 2-cycle pipelined multiplication unit spanning E and M stages: Reads inputs in E, produces outputs in M (available in W)