Electronic Design Integrity Check, PSpice Simulate, RF Simulate & PCB Layout -- 2

Circuit Analysis and PSpice simulation, board layout, RF simulation of PCB and back annotation, correction of files. Must be done in Cadence - Orcad - Allegro - PSpice. Cadence 16.3 or greater. Engineer must be 100% fluent in English and very familiar with relevant IPC standards for high-speed PCB layout including IPC 2141A – 2004. Please do not bid unless you are fluent in British/American/Canadian/European English, fluent in Cadence Orcad/Allegro,, fluent in the relevant IPC standards and able to do PSpice and RF parasitic PCB simulation. Please see the attached files for more details. Please fill out and return the included NDA to receive further detail for the requirements. Thank you very much. I look forward to working with you.