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barcelona, spain
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Tilmeldt februar 19, 2007
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Zoran J.

@zorjak

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PhD in Computer Science

I hold a Ph.D. in Computer Science, and for the last 2 years, my work is related to the optimization of data-intensive workloads (Machine Learning, Computer Vision, Genomics) and their acceleration with FPGAs. Before starting this job, I gathered more than 8 years of valuable experience in industry and academia in the area of hardware design (FPGAs) and processor microarchitecture. I am very passionate about technology, especially about Machine Learning, Algorithms and Computer Science in general, and I use every opportunity to push further the boundary of my knowledge in these fields.

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Erfaring

Postdoctoral Researcher

Barcelona Supercomputing Center,
apr. 2017 - Nuværende
Optimization of HPC applications (Machine Learning/Deep Learning, Genomics), and their acceleration with FPGAs. Development of the code that runs on the host CPU (C/C++/OpenCL) and FPGA acceleration cards (OpenCL) to increase application performance and reduce overall energy consumption.

Engineer Staff, IC design

Broadcom
jun. 2015 - maj 2016 (11 måneder, 1 dag)
Part of the international team in charge of the RTL verification of a custom made ARM core. This included, writing test plan, coverage driven and test driven arm assembly and system verilog test, debugging rtl ...

Research Assistant, PhD candidate

Universitat Politecnica de Catalunya
apr. 2011 - maj 2015 (4 år, 1 måned)
Research on the topic FinFET technology and cache memory design. This includes: characterisation of memory cells and proposing novel cache architectures to combat process variability and reduce power consumption.

Uddannelse

PhD of Computer Science

Universitat Politècnica de Catalunya, Spain 2011 - 2015
(4 år)

Master of Computer Science

Serbia 2008 - 2010
(2 år)

Diploma in Electrical Engineering

Montenegro 2002 - 2006
(4 år)

Kvalifikationer

Different Certificates

Coursera
2014
Coursework - Coursera, Udacity, Using Massive Open Online Course (MOOC) platforms, took courses from top universities (Stanford, John Hopkins, Michigan). Design and Analysis of Algorithms, Computer Architecture, Statistics, Data Analysis

Intel E.U. Doctoral Student Honor Programme Award

Intel Corporation
2013
Award given by the exceptional PhD students for the work in the field that is of the special interest of the Intel Corporation. 13 students awarded in E.U. in 2013

Publikationer

An example of flexible, FPGA-based median filter

International Conference, ETRAN
M. Zogović, G. Blagojević, Z. Jakšić, M. Jovanović, R. Stojanović, “An example of flexible, FPGA-based median filter ”, International Conference, ETRAN, Belgrade 2006

An approach to realization of FFT using FPGA technology

International Conference, ETRAN
Z. Jakšić„ M. Zogović, R. Stojanović, “An approach to realization of FFT using FPGA technology”, International Conference, ETRAN, Igalo, 2007

One example of implementation of high-speed packet communication in complex control systems

International Conference, ETRAN
Z. Jakšić, “One example of implementation of high-speed packet communication in complex control systems ”, International Conference, ETRAN, Donji Milanovac 2010

FPGA implementation of resource optimal CIC filter

International TELFOR conference
M. Nikolić, Z. Jakšić, “FPGA implementation of resource optimal CIC filter ”, International TELFOR conference, Belgrade, 2010

Enhancing 6T SRAM Cell Stability by Back Gate Biasing Technique for 10nm SOI FinFETs under Process and Environmental Variations

IEEE MIXDES
Z. Jakšić, R. Canal, “Enhancing 6T SRAM Cell Stability by Back Gate Biasing Technique for 10nm SOI FinFETs under Process and Environmental Variations”, 19th IEEE MIXDES Warsaw, 2012

Analysis of FinFET technology on memories

EEE IOLTS
E.Amat, A. Asenov, R. Canal, B. Cheng, J.-Ll. Cruz, Z. Jakšić, M. Miranda, A. Rubio, P. Zuber, “Analysis of FinFET technology on memories”, 18th IEEE IOLTS, Sitges 2012

nhancing 3T DRAMs for SRAM Replacement Under 10nm Tri-Gate SOI FinFETs

IEEE ICCD
Z. Jakšić, R. Canal, “Enhancing 3T DRAMs for SRAM Replacement Under 10nm Tri-Gate SOI FinFETs”, 30th IEEE ICCD, Montreal, Canada, 2012

Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Environmental Variations

Workshop on Resilient Architectures, Held in conjunction with MICRO-2012
Z. Jakšić, R. Canal, “Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Environmental Variations”, Workshop on Resilient Architectures, Held in conjunction with MICRO-2012, Vancouver, Canada, 2012

Comparison of SRAM Cells for 10-nm SOI FinFETs Under Process and Environmental Variations

IEEE Transactions on Electron Devices
Z. Jakšić, R. Canal, “Comparison of SRAM Cells for 10-nm SOI FinFETs Under Process and Environmental Variations”, IEEE Transactions on Electron Devices, January 2013

DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy

IEEE Design Automatization Test Europe
Z. Jakšić, R. Canal, “DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy”, to be published in IEEE DATE, Dresden, Germany, March 2014

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