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$20 USD / time
Flag for PAKISTAN
swabi, pakistan
$20 USD / time
Det er i øjeblikket 5:08 AM her
Tilmeldt januar 20, 2020
0 Anbefalinger

Sujjad A.

@sujjadaliyzi

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$20 USD / time
Flag for PAKISTAN
swabi, pakistan
$20 USD / time
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Genansættelsesrate

Electronics Engineer | IC Desginer

Hi! Thanks for visiting my profile I am an Electronics Engineer with master’s in Integrated Circuits (ICs), experienced in Analog and Digital circuits Schematic designing, Layouts and Simulations on 65nm,110nm and 180nm technology nodes. My projects, which best capture my expertise using the Cadence Virtuoso simulation environment to develop key analog IC building blocks including. • Opamps / OTAs • Comparators • Bandgap References • Current mirrors • LDOs • Level Shifters • Level Translators • Drivers • Memories (SRAM & DRAM) • Temperature Sensors • ADCs (SAR, Sigma Delta) • Ring oscillators In addition, I have experience with Digital ASIC design from RTL to GDSII using Encounter, Genus, Innovus, and Calibre for DRC, LVS and PEX verification. Also I have experience of Verilog based Implementation for Pipelined RISC-V Processor and Mesh based FPGA architectures. I’m a highly organized and self-motivated freelancer. I’ll be very happy to create a wonderful working relationship with You. Thank you for your consideration.
Freelancer Electronics Engineers Pakistan
Se alle Electronics Engineers i Pakistan

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Portfolio-mappe

11149105
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
11148364
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
9729853
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator
11149105
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
SRAM and DRAM design project Schematics, Layout and Simulation Results
6T SRAM and 1T DRAM Memory Project
11148364
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
A 12-bit pipelined and Time-interleaved SAR ADC, designed in Cadence Virtuoso with simulations results of ENOB=10.29 Bits and SNR = 63.71dB
12-Bit SAR ADC Simulation
9729853
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator
Clocked Comparator Schematic Rail to Rail Dynamic Latched Comparator Bootstrapped Switch for linear switching operations
StrongArm Latched Comparator

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Kvalifikationer

Web Designing and Development

National and Vocation Technical Training Commision
2017
I have my certification with distinction from NAVTTC Pakistan

Kontakt Sujjad A. omkring dit job

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Bedste færdigheder

Electronics
Matlab and Mathematica
Verilog / VHDL
Report Writing
Electrical Engineering

Gennemse lignende freelancere

Electronics Engineers in Pakistan
Electronics Engineers
Matlab and Mathematica Engineers
Verilog / VHDL Designers

Gennemse lignende fremvisninger

Electronics
Matlab and Mathematica
Verilog / VHDL
Report Writing
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