Design / ASIC / FPGA / Hardware Engineer with Embedded Programming experience.
Pruthvinath Reddy Sripathi neubaugasse 56/29.
08010 – Graz , Austria.
Ph : 0043 650 9022726
Profile
Ø Sep 2003 - Till Date Design Engineer , austriamicrosystems AG ,Graz. Austria.
Ø Apr 2002 - Aug 2003 Masters ( MSEE in Microelectronics ) , Technical University – Dresden, Germany.
Aug 2002 - Aug 2003 Research Asst , Mobile Communications Department. TU-Dresden.
Ø Apr 2000 - Feb 2002 Embedded Programmer at Real-time Controls Pvt Ltd. Bangalore.
Ø Jun 1996 - Mar 2000 Bachelors in Electronice & Communications Engg. India
Primary Skills
Ø 3 years experience with VHDL / Verilog / Simulation / Synthesis for ASIC / FPGA.
Ø gate level synthesis and simulation of Mixed signal circuit’s experience.
Ø experience in timing closure and static timing analysis ( STA ) with Synopsys Primetime.
Ø knowledge of low power digital design , synthesis and power estimation ( Primepower )
Ø knowledge of DFT, clock tree ,physical synthesis and adv. test pattern generation.
Ø advance verification with PSL at HDL and Logic Equivalence Check at netlist level.
Ø knowledge of formal verification techniques and usage of logic equivalence checkers.
Ø supporting the backend team for clock tree definitions and floor planning.
Ø Knowledge of generation of test patterns and problem solving with close interaction with test engineers.
Ø through understanding of different file formats ( netlists ,def, sdf, xcf, ucf etc ) for debugging
Ø 2 + years extensive experience with Xilinx and Altera fpga’s technology and toolset.
Ø advance FPGA toolset PlanAhead & Chipscope usage for faster project planning,debug and evaluation.
Ø experience in programming 8 /16 bit uC architectures and interfaces ( SPI, I 2 C, CAN).
Ø 2 + years programming experience in C, Embedded C, Assembly Programming.
Ø good knowledge of Digital Signal Processing, RF Trasmitter/Receiver architectures & evaluation.
Ø through understanding analog & digital communication systems.
Ø working experience with HP16500C Logic Analysers/Pattern generators.
Ø knowledge of CVN and SVN server, a multi site development environment.
Ø good knowledge of memory interfacing , IO standards, data converters and discrete components.
Ø through knowledge of tcl & perl scripting.
Special skills.
Ø ability to write highly portable, modular, scalable code in VHDL/ Verilog for portability, reusability.
Ø ASIC to FPGA and FPGA to ASIC migration experience for quick system evaluation.
Ø strong team building, facilitation and mentoring skills with the ability to work with cross functional teams.
Ø german engineering education and precision together with strong work ethics.
Ø strong project management and analytical problem solving skills.
Ø Strong motivation to learn and adapt quickly to new technologies and toolset.
Ø strong foundation in basic electronics , signal processing , RF architectures .
Experience
March 2005 – Till date in RF Group, austriamicrosystems AG, Graz.Austria.
Ø as digital design engineer was a member of an international cross-functional engineering team developing
low data rate RF-TRX for automotive industry.
Ø responsible for specifying and implementing digital blocks in VHDL/ Verilog
Ø use digital simulations for functional and timing verifications and responsible to prove full functionality of
digital part by backannotation.
Ø generation of final netlist on gate level by logic synthesis, advise layouters in finding optimal floor plans.
Ø design for testability incl. embedded test software, development of testbenches.
Ø performed measurements in the laboratory for prototyping, characterization, qualification and debugging.
Ø wrote the design specific documentation for internal and external use (i.e. design report).
Ø Carried out specification, design, and implementation and debugging of RF trans receiver ASSP on FPGA ( Spartan 2E, Virtex4 ).
Ø debugging and correction of third party VHDL with insufficient and contradicting documentation.
Ø FPGA setup and board bring-up and lab debugging in close interaction with firmware and board designers.
Ø design flow setup, scripts generation and CAD/EDA tool support and configuration.
Sep 2003 - Nov 2004 - Energy Metering Group, austriamicrosystems AG.
Ø Programming of an on chip std-8051 uC for single phase energy metering ASSP and evaluation.
Ø work included overall software definition, coding and testing of overall meter functions.
Ø generated custom monitor program for in system programming through serial interface.
Ø knowledge of debugging environment of Kiel – uVision.
Ø Design and implementation of 3-Phase energy metering application with AFE, uC and Xilinx FPGA.
Ø HDL code synthesised for xilinx fpga, developed uC code 3 phase metering functions.
Ø worked in close cooperation with board designers for design of analog front end (AFE).
Ø evaluated system for further improvements with Meter Test Equipment.
Ø achieved maximum of 5% error over a dynamic range of 60 mA - 60 A and 120V - 260 V.
Apr 2002 - Aug 2003 - Student VHDL Designer at Mobile Communications Department. TU-Dresden.
Ø HDL coding, simulation and synthesis of VHDL modules for M5DSP Processor.
Ø Behaviour modelling was carried out in C.
Apr 2000 – Feb 2002 - Embedded Programmer at Real-time Controls Pvt Ltd. Bangalore.
Real-time Controls specialises in analytical & medical instrumentation, Lab & Process and Bio-
Technology instrumentation. Was part of the Embedded Programming team and involved in development
and debugging of s/w modules. Mostly involved in programming for Intel std 8051 / 8085/8086 uCs and
and supporting device controllers like programmable Peripheral Interfaces, DMA
Controllers, Interrupt Controllers and Keyboard/Display Interfaces. Knowledge of embeddedC toolset
Kiel– uVision, HITEC C , MPLAB Integrated Development Environments.
Projects :- Web enabled on-line ambient air quality monitoring systems.
Web enabled real-time automatic weather stations.
Embedded system trainer kits.
Programming Skills
Ø HDL - VHDL, Verilog.
Ø Programming - C, C++, EmbeddedC, Assembly Programming (8/16 bit), Java ,HTML.
Ø Scripting – TCL / Perl.
Ø Basic Knowledge of Matlab Programming.
Ø Good knowledge of Unix & Windows environments.
Design Tools
Logic Synthesis Design Compiler, PowerCompiler , DFT Compiler, Buildgates.
Physical Synthesis Silicon Ensemble, FirstEncounter XL, Nanoroure Ultra, CTGEN.
Verification Primetime ( STA ), Conformal and Formality ( LEC) , ATPG , PrimePower.
Simulation Modelsim , NCSIM.
FPGA ise 7.1 , Chipscope , Planahead., Mentor - PrecisionRTL , Synopsys -FPGA compiler.
Embedded Kiel u-Vision , MPLAB integrated development environments.
Education
Ø MSEE in Microelectronics from Technical University Dresden.Germany.
Ø Bachelor of Engineering in Electronics and Comm. Eng from Bharathidasan University, India.
Miscellaneous
Ø Secured LEONARDO European scholarship for a period of one year.
Ø Attended “summer school microelectronic-02” jointly organised by Infineon Technologies, AMD and ZMD.
Ø Attended FirstEncounter XL and Nanoroute Ultra physical synthesis course from Cadence.
Personal
Ø Nationality Indian.
Ø Martial status Single
Ø Date of Birth 15th June, 1978.
References on request.
