Ellyptech H. Profile | Freelancer

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Tilmeldt november 21, 2011

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Ellyptech H.

@ellyptech

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Embedded developer

Professional with 11+ years of experience in cryptography, HDL and embedded systems. Architected technologically diverse projects and managed full project development cycle from Concept design to end product. My greatest strength is an analytical capability to grasp new technology/ current research and provide an innovative, efficient and optimum solution to the problem.

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Portfolio-mappe

Developed Fast boot image of Raspberry Pi for car dashboard application. Custom kernel was developed with stripped functionality for ultra fast boot requirement.

Fast boot image for Raspberry Pi (Under 5 sec)

Xilinx Virtex UltraScale+ FPGA VCU1525 based True Random Number Generator with throughput 20Gbps. System is being used as random source in various Monte Carlo simulations and Cryptography.

FPGA based True Random Number Generator

High-frequency trading (HFT) has been in a limelight during the past couple of years, turning into an increasingly important component of financial markets. HFT is all about the speed: faster the algorithm analyse stock exchanges and execute trade orders, higher is the profit. Here I am proposing an abstract architecture and design flow for such Low-latency strategies pipeline design.

https://github.com/shivamfpga/HFThdl.git

FPGA based HFT Accelerator (Proposal)

Xilinx Virtex UltraScale+ FPGA VCU1525 based SHA256 hash Accelerator with hash rate of 2.5 Giga hash/sec for Block chain acceleration. Design comprise of 128 parallel running cores over AXI stream bridged with host via QDMA (PCIe). With multiple cards in a rig.

FPGA based SHA256 hash Accelerator (2.5 Giga hash/sec)

Developed Fast boot image of Raspberry Pi for car dashboard application. Custom kernel was developed with stripped functionality for ultra fast boot requirement.

Fast boot image for Raspberry Pi (Under 5 sec)

Xilinx Virtex UltraScale+ FPGA VCU1525 based True Random Number Generator with throughput 20Gbps. System is being used as random source in various Monte Carlo simulations and Cryptography.

FPGA based True Random Number Generator

High-frequency trading (HFT) has been in a limelight during the past couple of years, turning into an increasingly important component of financial markets. HFT is all about the speed: faster the algorithm analyse stock exchanges and execute trade orders, higher is the profit. Here I am proposing an abstract architecture and design flow for such Low-latency strategies pipeline design.

https://github.com/shivamfpga/HFThdl.git

FPGA based HFT Accelerator (Proposal)

Xilinx Virtex UltraScale+ FPGA VCU1525 based SHA256 hash Accelerator with hash rate of 2.5 Giga hash/sec for Block chain acceleration. Design comprise of 128 parallel running cores over AXI stream bridged with host via QDMA (PCIe). With multiple cards in a rig.

FPGA based SHA256 hash Accelerator (2.5 Giga hash/sec)

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Mtech

India

2007 - 2009

(2 år)

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