DDR3 layout in Altium

Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.

PCB Layout Elektronik Elektrisk Ingeniørarbejde Kredsløbs Design Microcontroller

Projekt ID: #29354785

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