Profilbillede af arunaupul
@arunaupul
Flag of Sri Lanka Badulla, Sri Lanka
Member since 24. juli 2013
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arunaupul

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I'm an Electronic and telecommunication Engineer who graduated from University of Moratuwa Sri Lanka in 2015. I have 2 year working experience in developing digital designs for applications in Video-coding, Data-encryption and video broadcasting fields. I'm familiar with leading FPGA and ASIC development and verification tools such as Xilinx Vivado, Questa, Synopsis DC, and Lattice Diamond. I'm interested in design and develop digital systems using System-verilog/VHDL and verification using C models.
$5 USD/t
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3.1
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Portfolio

Seneste bedømmelser

  • image of lokhmanmunnu project with c $225.00 AUD

    “Awesome Work”

  • image of malitehseen Vivado Xilinix 2016.4 Project (VHDL and C language) $250.00 AUD

    “He was very helpful and completed my work on time and also gave me time to explain what he has done. He will replay to my quires as soon as possible and give me updates about the work on regular basis. Excellent work.”

Erfaring

Electronic Engineer

Jul 2015

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Uddannelse

Electronic and Telecommunication Engineering

2010 - 2015 (5 years)

Publikationer

Implementation techniques for IEEE 802.3ba 40Gbps Ethernet Physical Coding Sublayer (PCS)

The Physical Coding Sublayer (A sublayer of the Physical Layer of OSI 7 layer model) of the 40Gbps Ethernet Standard was implemented in RTL coding and tested as the final year project for my graduation.

Certificeringer

  • C 1
    83%
  • Digital Electronics Level 1
    78%

Verifikationer

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