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Anju G.

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M.Tech in VLSI

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India (11:55 PM)

Tilmeldt marts 16, 2007

Graduate in VLSI, and having cutting edge exposure from minarc, ISEP, Paris in microelectronics. I am here to broaden the horizon of the challenges. I have published a paper in IEEE-TED.

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Bedømmelser

Ingen bedømmelser at se her!

Erfaring

Contract engineer

okt., 2007 - jun., 2008

8 måneder

DRDO

okt., 2007 - jun., 2008

8 måneder

I was involved and evolved in developing in web pages and developing the online web pages for the company.

okt., 2007 - jun., 2008

8 måneder

Uddannelse

Vellore Institute of Technology

2008 - 2010

2 år

M.Tech

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India

2008 - 2010

2 år

Visvesvaraya Technological University

2002 - 2006

4 år

B.E.

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India

2002 - 2006

4 år

Kvalifikationer

Designing

2010

Paper publishes in designing in IEEE-TED

2010

Udgivelser

30nm Tunnel FET with Improved Performances and Reduced Ambipolar Current, published in IEEE-TED (Transaction on Electron Device), TRANSACTIONS ON ELECTRON DEVICES

Anju Gupta

To boost the on current with the source edges.

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