Tarek A.

Hi, ✅ I'm experienced in FPGA, ASIC design using Verilog and System Verilog HDL. ✅ I'm also experienced in Analog/Mixed signal IC Design using Cadence Virtuoso. ✅ I'm also experienced in various tools eg: MATLAB, COMSOL Multiphysics, ISE/Vivado, Modelsim/Questasim, Design compiler/IC compiler and others. ✅My experience in ASIC and FPGA design is summarized in the following projects: - RTL design of a single cycle, multi cycle and pipelined ARM processor with Data path unit, control logic and hazard unit using system Verilog. - RTL design of gray code counter which was then deployed on Altera FPGA - RTL design of an ALU that perform 16 different operations. ✅My experience in Analog IC design is summarized in the following projects: -Miller OTA. -Band gap reference. -folded cascode OTA.