Profilbillede af IlyaRuff10
@IlyaRuff10
Medlem siden 12. august 2015
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IlyaRuff10

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I am electronics and wireless communication engineer. An expert with more than 5 years experience on FPGA Design using Verilog HDL. My skills: C /C++, MatLab, Simulink (with System Generator), Verilog, Python. I have extensive experience with Mentor ModelSim, Xilinx ISE Design Suite, VIVADO Design Suite, MatLab / Simulink (with System Generator);
$8 USD/hr
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