I have some verilog files I need some work on. In the attached folder there is a verilog project called keyboard_top which is a SP/2 decoder for the arrow keys on a keyboard. I need the output from the arrow keys to be changed from individual outputs to one output as a 3 bit. (001 for up, 011 down, 101 right, 110 left.). Then I need the 3 bit output to be concatenated to a 16 bit value. There is a text file called keyinflop that has a 16 bit concatenation that can be used.

Then make sure all modules are being instantiated in the keyboard_top module.

I need a test bench to make sure it is working

Then I need that keyboard_top connected into the maze3710 project. Instanuate it in the VGAProcessor module and connect the 16 bit concatenated arrow key output value to the keyIn

Evner: Verilog / VHDL

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Om arbejdsgiveren:
( 3 bedømmelser ) Sandy, United States

Projekt ID: #22407805

8 freelancere byder i gennemsnit $122 på dette job


Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss

$166 USD på 1 dag
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Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 6 years. Please let me know if the requirement is still there I can work on it. Thanks

$155 USD på 1 dag
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Hello sir/ma, I'm interested in taking this task up for you. I am an Electrical Engineer with a masters degree and I have high proficiency knowledge in FIRMWARE: FPGA firmware in VHDL and Verilog for Altera/Actel/Xilin Flere

$40 USD på 1 dag
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Electronics Engineer with experience in large scale complex systems development with practicing in Verilog, SystemVerilog and Programming Firmware, C, C++. Let's Discuss further.

$50 USD in 10 dage
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Hello, I have gone through your job posting and become very much interested to work with you. I am an expert in this field. I have already completed several projects like this. For evidence you can see my profile. Pl Flere

$250 USD in 7 dage
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I have much experience in device manufacturing such as PIC, Arduino, STM-series(ARM), FPGA,CPLD,etc. I love Math & Physics. Using FPGA based on Verilog/VHDL Language, I completed several projects including Synchronizat Flere

$30 USD på 1 dag
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Hi I have experience in RTL Design . I can provide you with the verilog code and testbench. Also has an experience in SoC integration. Will deliver the complete design in time

$166 USD in 2 dage
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$122 USD på 1 dag
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