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Simple Neural Evaluation -- 2

The EE 272 Simple Neural Evaluation engine takes weights for a neural network, and applies them to

input data. The design is flexible, and assumes very little about the neural network. This design

assumes all data is contiguous and all weights are processed. The design assumes the input data is 24

bits per sample in 2’s complement form. For math reasons, the input number are commonly scaled to

be between -1 and +1. This implies the data is actually 8.24 binary fixed point. This scaling is

important when processing weights. The weights are assumed to be in 8.24 form. (32 bits fixed binary

point) The neural network can have up to 4096 inputs per layer, and this adds 12 additional bits to the

sum. There can be up to 4096 nodes per layer. The input data is mapped to 8.24 before operation. The

8.24 x 8.24 multiplications result in 16.48 intermediate values which are summed to be 28.48 binary

fixed point. After summing all products, the result is reduced to 8.24 by saturation. The data is then

applied to a neural function. (a table lookup assumed to be the sigmoid or tanh function) To simplify

the design, all neurons are assumed to be the same in each layer. The neuron result becomes the input to

the next layer, or the output from the last layer.

The design runs at a clock rate of 300 Mhz. (Use design ware multi stage pipelined multipliers at this

speed). The design performs 16 multiplies each cycle in the weight calculations. This requires a

pipeline fetching weights and data, performing operations, and calculating the final sum. To support

this performance level, data are stored in a memory which is 16*32 (512 bits wide). Each memory has

up to 4M 512 bit words (24 bit address). The actual number of words is a system Verilog constant

contained in the “[login to view URL]” file. There is one memory for calculation data, and one memory for

weights and configuration data. The memory is pipelined and can only perform a read or write each

clock, Not both! Your design will require arbitration to decide if a read or write will happen to the

memory.

Evner: Verilog / VHDL, Digital Design, Neural Networks

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