Recursive karatsuba multiplier (16bit)

₹1500-12500 INR

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cirka 6 år siden

₹1500-12500 INR

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I need a verilog code for recursive karatsuba multiplier for 16bit signed integers.

Digital Design

Verilog / VHDL

Projekt-ID: 16210126

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6 forslag

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Aktiv 6 år siden

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@mastor31

Hi, I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera. Please elaborate your requirement to proceed further. Regards, Chhanda

₹4.000 INR på 3 dage

5,0

(9 anmeldelser)

4,1

6 freelancere byder i gennemsnit ₹12.472 INR på dette job

@ahmedmohamed85

A proposal has not yet been provided

₹13.888 INR på 1 dag

5,0

(309 anmeldelser)

7,6

@SANGITAR

I have proficiency with VHDL and Verilog. I am good with Xilinx and Altera FPGA. Are you referring any IEEE paper

₹16.666 INR på 30 dage

5,0

(3 anmeldelser)

4,1

@olegkaravaev84

I have more than 10 years of an experience in the FPGA/ASIC design and also I have an experience in the implementation of a mathematical algorithms.

₹12.500 INR på 2 dage

5,0

(3 anmeldelser)

3,6

@yemelitc

Hello, This is a rather tricky project, so I raised the reward. Any particular reason for that algorithm on just a 16bit signed integer? But anyway as a Verilog HDL programmer and one who knows the algorithm, I can do your project. I specialise in the field of reconfigurable computing, in which I use Verilog HDL very often. For hobby I do a lot in algorithms. Do check my profile. Please note that I will need you to create a milestone if awarding me the project.

₹20.000 INR på 2 dage