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Need someone good expert in computer architecture -- 3

Need someone good expert in computer architecture

In this project, you will be implementing a pipelined MIPS processor datapath with the following features:

1) FDEMW 5-stage pipeline with branch resolution in D. Non-memory hazard detection in D.

a) 2-cycle pipelined multiplication unit spanning E and M stages: Reads inputs in E, produces outputs in M (available in W)

Evner: Verilog / VHDL, C programmering, Montage, C++ Programmering, Ingeniørarbejde

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Om arbejdsgiveren:
( 51 bedømmelser ) NANDGANJ ghazipur, India

Projekt ID: #32254637