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grayscale image processing in Verilog

Image processing in verilog.

2 DIFFERENT IMPLEMENTATIONS IF POSSIBLE.

grayscale image processing.

Objectives :

Implement in Verilog a synchronous sequential circuit which processes the grayscale images ( with a single color channel on 8 bits) . The images have a 64x64 bytes dimension.

Requirements:

[url removed, login to view] on the image a blur filter type

[url removed, login to view] of image mirroring.

[url removed, login to view] of picture rotation (90degrees)

Blur filter which needs to be implemented is gave by the following matrix:

{0,1,0 ; 1,1,1 ; 0,1,0}

Interface to be used:

module process(

input clk, // clock

input [1:0] op, // 0 – blur type filte; 1 - mirroring; 2 - rotate

input [7:0] in_pix, // pixel value from the position [in_row,in_col] for the used image

output [5:0] in_row, in_col, // selects one row and one column from the image

output [5:0] out_row, out_col, //selects one row and one column from the resulting image

output out_we, // activates writing for the resulting image (write enable)

output [7:0] out_pix,

output done // sends a done signal when image processing is complete

);

This module will also interract with the image module, which has the following interface :

module image(

input clk, // clock

input[5:0] row, //

input[5:0] col, //

input we, // write enable (activates writing)

input[7:0] in, // value of the pixel which will be written on the current position

output[7:0] out // value of the pixel which will be read from the current position

);

In the attachment you can download the interfaces.

Evner: Verilog / VHDL

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Om arbejdsgiveren:
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Projekt ID: #11843312

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