FSM in verilog

Færdiggjort Opslået 4 år siden Betalt ved levering
Færdiggjort Betalt ved levering

I have been tasked to write a FSM in verilog. The details are in the attached file. I have also attached a previous code I wrote to change ASCII into 7 segment displays, as I know that will be helpful to completing the FSM.

Verilog / VHDL FPGA Ingeniørarbejde Java Montage

Projekt ID: #21664923

Om projektet

4 bud Remote projekt Aktiv 4 år siden

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mrmarwan16

Hello, I am a senior student of electronic engineering, I have this project done in VHDL, I just need to translate it to Verilog, in a few hours it can be done quietly with its simulation. You can contact me with confi Flere

$25 USD in 7 dage
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4 freelancere byder i gennemsnit $74 timen for dette job

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Flere

$100 USD på 1 dag
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6.4
Valuesolutions

Hello, i have read the details provided..please contact me to discuss more on the project deadline and some other few things

$120 USD in 7 dage
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5.5