Færdiggjort

FPGA designer in VHDL, DO-254 project

Budget €18-36 EUR / time

Job Description:

Good knowledge of VHDL is required.

Libero Soc and Microsemi will be used

The simulator will be Aldec Active-HDL, linting with Aldec Alint

Design of a basic control board, standard interfaces, no high speed interfaces, no transceivers. DO-254 DAL C, basic knowledge is a plus

some math algorithm in fixed point will be implemented on the hardware for motor control

Supervision of our expert designers, short daily meeting and 1h weekly with reports on activities and scheduling

contract will be extended month by month (we have budget for 6 months).

Færdigheder: Verilog / VHDL, FPGA, DO-254 Certification

Om klienten:
( 0 bedømmelser ) LIVORNO, Italy

Projekt ID: #35257861

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Tildelt til:

ahmedmohamed85's Profilbillede
ahmedmohamed85

(471 bedømmelser)
8.0

5 freelancere byder i gennemsnit €226/timen for dette job

athulb's Profilbillede
athulb

Hi, I am having 5 years of experience in FPGA design, please check my profile for more details. I have used Libero Soc for IGLOO2 FPGA(Microsemi) so I'm familiar with the tool. Please consider my profile, and have a Flere

€27 EUR / time
(12 bedømmelser)
3.4
waletechs's Profilbillede
waletechs

Hi there! My name is Fernando and I'm interested in your project. I'm a Senior FPGA Designer/Developer with advanced knowledge of Digital Signal Processing and a Senior Electronic Engineer with 10+ years of experien Flere

€36 EUR / time
(0 bedømmelser)
0.0