Build small educational Quartus project to illustrate Altera SDRAM IP usage in VHDL on FPGA

Board : Terasic DE10-Lite MAX10 10M50DAF484C7G

- 2 push buttons

- 10 switches

- 6 7-segments

- 1 SDRAM module (ISSI IS4216320D)

- see [url removed, login to view] for more details about the board

Software tool : Altera / Intel Quartus Prime Lite 16.1

Project : create a small, minimalistic, Quartus project to illustrate the use of PLL and SDRAM IP libraries.

Description :

1) the user turns on or off each switch and defines a 10bit number

2) the user push the number into the SDRAM by pressing button #1

3) the user reads the numbers pushed into memory into the 7 segments by pressing button #2

Essentially that's it. Need well written, well documented, clean code.

Delivery : you deliver a minimalistic quartus project files, which I can open (*), compile it, and burn it to the board and play with the switches/button/7 segments.
(*) I am running Quartus Prime Lite 16.1 on Linux.

All the necessary IP libraries parameters (eg timings for the SDRAM wizard, Qsys project connections...) should be made available.

** Please do not use Nios processor design **

Evner: FPGA, Verilog / VHDL

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Om arbejdsgiveren:
( 0 bedømmelser ) Singapore

Projekt ID: #16750282

Tildelt til:


Dear sir I have more than 10 years experience in digital design using vhdl, please check my profile also please message me

$166 USD på 1 dag
(322 bedømmelser)