It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process.
-Structural and behavioral codes for the binary divider using VHDL.
-Testbench code testing as many divisions as possible. Different inputs that output different
quotients and remainders should be tested too.
-Synthesis of written code and verified post-layout simulation.
-Fastest and most-efficient architectures.
-Added features e.g. signed and floating point division.
12 freelancere byder i gennemsnit $40 på dette job
As a computer engineering student I have experience with VHDL student projects. Project will be written for Spartan-6 architecture, synthesizable, well tested and documented.
I have 15 years of VHDL design experience. I've been teaching for several years. I've done the SDR projects. I know how to write an optimal vendor independent VHDL Codes.
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