4-bit vhdl divider

It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process.

-Structural and behavioral codes for the binary divider using VHDL.

-Testbench code testing as many divisions as possible. Different inputs that output different

quotients and remainders should be tested too.

-Synthesis of written code and verified post-layout simulation.

-Fastest and most-efficient architectures.

-Added features e.g. signed and floating point division.

Evner: Verilog / VHDL

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Om arbejdsgiveren:
( 0 bedømmelser ) Donggang, China

Projekt ID: #19943939

12 freelancere byder i gennemsnit $40 på dette job


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$50 USD på 1 dag
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I have expertise in VHDL since 4 years and have enough exposure various Arithmetic Digital Circuit designing.

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