Nano VLSI Hetero Junction Transistor Optimisation

@bojans9

Namaste Bojan I understand you need to optimise a heterojunction tunnel FET for nano‑VLSI, improving drive current and reducing leakage while keeping thermal limits safe. With over ten years in circuit design, FPGA prototyping and thermal analysis I will model the device in TCAD, run bias simulations, tune the doping profile and extract the best layout for your process node. The result will be a validated design ready for silicon implementation and a report with performance curves and layout guidelines. I can deliver this within 7 days for 22,500 INR. Could you share the target supply voltage and expected on‑state current? Which TCAD tool do you prefer? Do you have thermal budget limits for the chip?

@Hmdlawal

HI, KINDLY READ THROUGH MY PROPOSAL Your PhD work needs more than TCAD simulation: the key is identifying a defensible research gap, defining HJ-TFET optimization parameters, then proving improvement through structured Silvaco TCAD results. I’m a VLSI/TCAD engineer with 6 years of relevant experience. I can develop the research path from literature-gap analysis and device structure selection through ATLAS modeling, calibration, parameter optimization, I-V/subthreshold analysis, benchmarking, and final result interpretation. I’d also validate which parameters are worth optimizing before simulation to avoid unnecessary runs. PLEASE INITIATE A CHAT I look forward to collaborating with you on this project.