Power optimize Algorithm in FPGA design

Hi all I'm having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isolation, clock gating, pipeline schedule... As you see, this work is not easy. However in simple case you can only give some links/advice that maybe help me. And certainly the work cost is belonged to what you have.

## Deliverables

1) In simple case, only some useful links that do something as my work need 2) you can give me your program source code (written by yourself or other) with document guide. (Payment will be much higher)

## Platform

Must compatibility with Altera and Xilin design enviroment (VHDL, netlist and simlation file results are from here).

Evner: PHP

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Projekt ID: #3319661

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