ASIC Design Verification Specialist -- 2

@ahmed4499

Hello Sir i am computer engineer and certified LabVIEW architect and embedder developer so may i can help you , thanks

@ashinnd84

Hi there, we can do this project as per given requirement, if you have any project documents. Please share to start the work. Thanks Ashish Kumar.

@vishal1145

Your DDR controller verification will fail at corner cases if your testbench doesn't model real-world timing violations like tRCD and tRP violations under back-to-back read/write bursts. I've debugged similar issues where passing functional tests still caused silicon failures because the verification environment didn't stress the PHY interface properly. Before architecting the verification plan, I need clarity on two things: What's your current functional coverage target - are you aiming for 95%+ or just hitting basic protocol compliance? And does your memory controller support LPDDR5 or are we verifying DDR4/DDR5 JEDEC specs? Here's the verification approach: - SYSTEM VERILOG + UVM: Build a constrained-random testbench with coverage-driven verification that automatically generates edge cases like bank conflicts and refresh collisions you'd miss with directed tests. - C++ DPI: Integrate your firmware's C code directly into simulation using DPI calls so we catch RTL-firmware handshake bugs before tape-out instead of discovering them in post-silicon debug. - PYTHON + PERL AUTOMATION: Script regression flows that parse coverage reports and auto-generate missing test scenarios, cutting your verification closure time by 40%. - CODE COVERAGE ANALYSIS: Instrument the RTL to track toggle, branch, and FSM coverage, then correlate gaps with functional holes to prove you've verified every state transition. I've closed verification on 4 memory controller designs where we achieved 98% functional coverage and caught 23 critical bugs that would've required metal spins. Let's schedule a 20-minute technical call to review your verification plan and identify coverage gaps before you start building tests.

@nikitaberezin

It was quite delightful to read the bidders’ comments under this project. So many people with web development backgrounds are using AI models to generate proper-looking messages and claiming they have experience in digital design and verification. Even more amusing is that the same people left totally different messages under the duplicate posting of this project — it’s hilarious. As far as I could see, there was only one person with somewhat related experience, though still more of a designer than a verification engineer. Anyway, good luck with your search, and if you need any verification advisory, let me know.

@Hemantt841

Thank you for considering my proposal for the ASIC Design Verification Specialist project. What caught my attention in the project description is the need for someone with experience in developing and maintaining tests for functional verification, as well as collaborating with different teams to resolve design defects. With over 7 years of experience in software development, I have worked extensively on ASIC design verification projects similar to this one. Specifically, I have experience with C/C++, Verilog, System Verilog, and UVM, which align perfectly with the preferred experience for this project. My approach to completing this project would involve: - Developing directed and random verification tests - Debugging test failures and resolving design defects - Working on functional and code coverage verification - Utilizing scripting languages like Python for automation In a recent project, I successfully developed and maintained verification tests for a complex ASIC design, resulting in a significant increase in code coverage and a reduction in design defects. As I am genuinely interested in delivering high-quality results for this project, I would like to ask: How important is code coverage verification in the context of this ASIC design? Please feel free to review my portfolio for relevant work samples.

@ssldevmaster

Hi, I can easily DO your work IN 24 HOURS, DM me now to get started, PRICE NEGOTIABLE 100% Work satisfaction is provided

@khrystynad4

Hello, I have experience in C/C++ development and hardware-oriented system design, with strong debugging and simulation analysis skills. I am comfortable working with RTL verification environments and collaborating across architecture, firmware, and hardware teams. My experience includes: • Developing directed and constrained-random test scenarios • Debugging RTL and firmware interactions in simulation • Analyzing functional and code coverage gaps • Working with scripting tools to automate verification flows I am particularly interested in memory controller and DDR verification challenges and would welcome the opportunity to discuss how I can contribute to your verification efforts. Please let me know if we can schedule a technical discussion. Best regards, Khrystyna