Hi there!

I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project which can be found in section 3.1 of uploaded pdf (round-based based architecture of PRESENT-80).

The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so that I can perform power analysis on it. Need the code properly working in two days.

I looking for a Clock based implementation on existing design

Language used : VHDL

Evner: Elektrisk Ingeniørarbejde, Ingeniørarbejde, FPGA, Java, Verilog / VHDL

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Om arbejdsgiveren:
( 0 bedømmelser ) Ireland

Projekt ID: #17597728

4 freelancere byder i gennemsnit €47 på dette job


Hi, I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera. I believe I am the best person f Flere

€50 EUR på 1 dag
(12 bedømmelser)

Hello My friend, I Ahmed Zaky, Senior Nanoelectronics Engineer. I have worked with PRESENT algorithm before and I know how it works very well. I can help you with making both the encryption and decryption in Verilo Flere

€8 EUR på 1 dag
(7 bedømmelser)

Dear, I have checked your project description. I have an experience in device interface with ARM&FPGA and I have real devices. If you need to test on designed board, I will do it in a short time. I can confident Flere

€111 EUR på 1 dag
(0 bedømmelser)

I'm an Electronics engineer with great knowledge in FPGA systems and VHDL. I will develop the design in one day.

€20 EUR på 1 dag
(0 bedømmelser)