Enable dynamic clock tuning on Xilinx FPGA design

Have a design that is synthesizable and works properly on FPGA (nexys video - artix-7 based).

The clock is set via clock wizard, and I need to make it flexible without the need to regenerate bistream every time.

The dynamic clock setting can be done via "sw" pins (nexys video has 8 sw pins on board).

When new clock frequency is set, the expectation that design will reset and restart operation once the new clock frequency is stable.

Bonus - If you can also enable this flexibility via python script when FPGA is connected with USB (so the clock control registered will be programmed directly from PC).

Evner: FPGA, Verilog / VHDL

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Om arbejdsgiveren:
( 0 bedømmelser ) United States

Projekt ID: #20433082

17 freelancere byder i gennemsnit $234 på dette job


Dear sir I have more than 10 years experience in digital design using FPGA I can do the required design, please message me so that we can discuss

$250 USD in 3 dage
(394 bedømmelser)

Hi. I'm FPGA based Embedded system Engineer. I have worked on dynamic clock synchronization. I can set the clocking values via switches or any other required peripheral. I can also sync your design according to the new Flere

$190 USD på 1 dag
(12 bedømmelser)

Hi Its possible to do this so that you can configure the clock from a pc. That way you can set any frequency you want within the range of the MMCM. Regards Jon

$200 USD in 3 dage
(2 bedømmelser)

Hi there, I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the Flere

$155 USD in 3 dage
(1 bedømmelse)

Hi! I'm interested in your project and I have a few questions: - What is the language of your project? (VHDL or Verilog?) I'm more comfortable with VHDL (I've done a similar task in my project in VHDL), but I'm also a Flere

$200 USD in 12 dage
(1 bedømmelse)

A Data Scientist with experience in Python, R programming, R Shiny, R studio and anything related to data science and python Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourc Flere

$140 USD in 7 dage
(1 bedømmelse)

Hello there, i have the ARtix-7 FPGA board with me and i have good expertise with VIVADO and VHDL/Verilog based design flow. I have worked on clock pre--scaling project many times. So i can do your project with dynamic Flere

$200 USD in 7 dage
(1 bedømmelse)

Hello, I have read the details provided and i am positive i can provide quality work,please contact me to discuss more on the project deadline and some other few things

$120 USD in 4 dage
(0 bedømmelser)

I can write the VHDL code for the FPGA that gets the clock rates as inputs thru sw pins and set the loops accordingly. I would do it with lower cost if it only needs to set the clocks w/o other functionalities. We may Flere

$166 USD in 7 dage
(0 bedømmelser)

Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 5 years. Please let me know if the requirement is still there I can work on it. The price mentioned is negotiable according to your requ Flere

$333 USD in 5 dage
(0 bedømmelser)

I already have this tested module ready with me. The only problem is integrating with USB because I do not know what interface you use. I have tested using Cypress controller. I have Kintex-7 based implementation using Flere

$200 USD in 7 dage
(0 bedømmelser)

I can do this I have specialization in following: Embedded System Design based on • Digital System Design (FPGA, CPLD) • Signal and Image Processing Algorithms • Micro-Controllers & Processors  Hands on experience o Flere

$30 USD in 7 dage
(0 bedømmelser)

Wow, Wonderful! I met the first FPGA project in freelancer :) I am FPGA (VHDL) expert! so I can help you. I 'd like discuss with you via chatting. I will wait. Thank you! From Apollo!~

$1000 USD in 7 dage
(0 bedømmelser)

Hi, I am having 28+ years of rich R&D experience in Embedded Hardware systems, FPGA based systems, Circuit design, Validation, Microprocessor/ Microcontroller based design Analog & Digital hardware design, Logic Desig Flere

$168 USD in 7 dage
(0 bedømmelser)

Hi, Are you using an MMCM or PLL to generate the clock? Either way, both primitives support dynamically changing the frequency by adjusting the Multiplier and Divider ranges of the primitive. What frequency range do y Flere

$233 USD in 10 dage
(0 bedømmelser)

Interested with the project, Design engineer with experience in large scale complex system design with practicing in Verilog, SystemVerilog, Programming firmware, C, C++ programming and Machine Learning with Python. Flere

$250 USD in 20 dage
(0 bedømmelser)

Hi, I understand your requirements. I an a design engineer in xilinx Apps Team, I have worked on xilinx RFSOC Target reference design as well as VCU Target reference design for ZCU111 and ZCU106 Boards respectively. I Flere

$150 USD in 7 dage
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