I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, will result in no change of system. And of course, machine language codes. This will be used to teach an AP class. System Verilog.
[login to view URL] is a great example of what I am looking to teach with an FPGA