VLSI Physical Design Using Innovus

I have a block-level design that now needs to move through the physical flow. The immediate milestones are clear: create an efficient floorplan, push the design through detailed and global routing, and close out with verification. All work must be driven in Cadence Innovus; please be comfortable setting up and iterating flows entirely in that environment. Design rules are not locked down yet. I will share the process kit, but I’m open to your recommendations on spacing, aspect ratios, congestion targets, and any additional constraints you feel are prudent for timing or power closure. In short, if you see a smarter set-up, propose it and we will adopt what makes sense. Deliverables • Innovus database and scripts for each stage (floorplan, routing, verification) • Reports for timing, power, and DRC/LVS at every hand-off • A brief summary of the decisions made and trade-offs considered so I can reproduce or extend the work If you have a proven track record hitting timing on advanced nodes with Innovus, I’d love to review a snapshot of past reports or screenshots. Let’s get this design physically clean and sign-off ready.

Project ID: 40544130