VHDL Verification Engineer -- 2

Lukket Opslået 4 måneder siden Betalt ved levering

Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs.

Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.

Ingeniørarbejde Elektronik Verilog / VHDL Elektrisk Ingeniørarbejde FPGA

Projekt ID: #36673609

Om projektet

7 bud Remote projekt Aktiv 2 måneder siden

7 freelancere byder i gennemsnit €30/timen for dette job


Hi there,I'm biddin on your project "VHDL Verification Engineer -- 2"Verilog / VHDL, FPGA, Engineering, Electrical Engineering and Electronics Campera Electronic Systems is planning to introduce a Verification methodol Flere

€46 EUR / time
(41 bedømmelser)

Hi there

€27 EUR / time
(4 bedømmelser)

Dear Andrea C. We went through your project description and it seems like our team is a great fit for this job. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, E Flere

€27 EUR / time
(1 bedømmelse)

I am excited to submit my proposal for the job opening at Campera Electronic Systems, where you are seeking a professional with experience in implementing verification methodologies for VHDL designs. Having extensive k Flere

€23 EUR / time
(0 bedømmelser)

I am a student from Indian Institute of Technology (IIT) Jodhpur with Computer Science and Engineering branch. I have been interested in Digital Electronics and have also completed a course in it with A grade. I would Flere

€20 EUR / time
(0 bedømmelser)