Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions.
Some is the work that I have done so far. I am currently working on the execute part and it only works for 101 cycles and not 4000 as instructed in the video.
Have to finish this four parts
Using my execute code, I am stuck on the execute part as it only performs 101 cycles and not 4000.
Contact me for documents
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Dear sir I have more than 10 years experience in digital design using verilog, please check my profile also please message me so that we can discuss Best regards