This project requires you to develop a high-speed FPGA design for integer division. Only those who have experience in Matlab, xilinx and system generator the apply. Otherwise please don't. Deadline is Monday and the budget is $50. I'll provide the template and algorithm and implementation process.
Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or 10 64-bit are the assumed platform.