I need some help on a Altera FPGA testcase.
A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO.
Written in Quartus 18.1 with Verilog/System Verilog.
And a testbench for verification.
The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip enable (active low) for the data bus to be enabled for read/write and a pin that indicates FIFO has reached its 3/4 capacity.
Inside the FPGA will be a single FIFO with 1024 words that data will be written to it via the 16bit bus and read again via the 16bit bus. FIFO will have 48bits word length.
What is required is the complete Quartus project with source rtl files and a testbech to verify the proper behaviour of the design.
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