Design Digital Alarm clock] using verilog

Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23). o Whenever the “alarm set” switch is on (SW2), the 6-digit 7-segment display should display the alarm setting rather than the current time. o Whenever the “alarm clear” button (KEY0) is pressed, the alarm should be reset to 0. ▪ KEY0 takes priority over SW2 meaning that if it is pressed while SW2 is active, the alarm should be reset to 0. • Timing / Clock generation o The alarm clock should be accurate. Divide down the 50MHz clock at PIN_M9 as necessary to achieve this (on the FPGA). You are not expected to verify that your clock keeps good time. For all Frequency dividers use a 50% duty cycle. This should be constructed similar to a counter. 50% duty cycle means the output clock, the result of dividing down, should be logic 1 half the time and logic 0 half the time. The grader will check this in your waveforms. • Switch functions o SW0 will act as a reset. Both the time and the alarm time should be reset to zero if SW0 goes active. SW0 has priority over any other switch o SW1 is the “time set” switch. When it is on, the display freezes at whatever the time was when the button was pushed, and by pressing KEY1, KEY2 and KEY3 now, one can set the time to a new value. o SW2 is the “alarm set” switch. When it is on, the display shows whatever value the alarm is currently set to (which should be 0000 after reset) and can be adjusted with KEY1, KEY2 and KEY3 as described below. o SW3 is the “alarm activated” switch. It must be on for an alarm to occur. o SW4 is a 120x speed demo/debug mode. In this setting the minutes will increment at a half second speed. Use this when setting minutes and hours. o KEY1 – When either SW1 or SW2 are active, this switch causes the second characters to count up at about a half second rate so that one can set the seconds on the clock 2 o KEY2 – When either SW1 or SW2 are active, this switch causes the minutes characters to count up at about a half second rate so that one can set the minutes on the clock o KEY3 - When either SW1 or SW2 are active, this switch causes the hours characters to count up at about a half second rate so that one can set the hours on the clock 3 • LED functions o LEDs 0-4 should turn ON whenever the corresponding switches are on. o LED7 is essentially the alarm. Whenever the clock time becomes equal to the alarm time, this LED should blink ON until KEY0 is pressed to clear the alarm. • Button functions o If the alarm went off because the clock time equaled the set alarm time, pressing KEY0 will clear the alarm and LED7 will turn OFF. • Other Considerations o SW1 and SW2 are mutually exclusive (one-hot). Only one should be active at a time. If both are active at the same time, the behavior should be the same as if neither of them was active. o Whenever the “alarm set” switch is on, or when the KEY0 is pressed, time should continue to input SW0, input SW1, input SW2, input SW3, input SW4, input KEY0, input KEY1, input KEY2, input KEY3, output reg [6:0] HexSECOND_LSB, output reg [6:0] HexSECOND_MSB, output reg [6:0] HexMINUTE_LSB, output reg [6:0] HexMINUTE_MSB, output reg [6:0] HexHOUR_LSB, output reg [6:0] HexHOUR_MSB, output reg LED0, output reg LED1, output reg LED2, output reg LED3, output reg LED4, output reg LED7 ); This top module should display the HexSECOND_LSB, HexSECOND_MSB, HexMINUTE_LSB, HexMINUTE_MSB and HexHOUR_LSB, HexHOUR_MSB on 7- segment display of FPGA.