Lattice ispLSI1032 CPLD Reverse Engineer Project

We are in the process of reworking an old design that used a Lattice ispLSI1032 CPLD. Unfortunately we no longer have any source files. All we have is a JEDEC file that we currently use to program CPLDs.

We contacted Lattice to ask about moving from the older design in to a newer CPLD and they said without any source files it would be impossible. So we are researching if anyone has ideas for a solution to reverse engineer the CPLD in to either a schematic or new source files/code.

Please review the attached JEDEC file. Any and all input or ideas are welcome, and any viable leads or assistance will be rewarded.

Please ask if there are any questions. Thanks!

Evner: Elektrisk Ingeniørarbejde, Elektronik, Ingeniørarbejde, Verilog / VHDL

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Om arbejdsgiveren:
( 6 bedømmelser ) Cherry Hill, United States

Projekt ID: #6055365

8 freelancere byder i gennemsnit $1448 på dette job


Dear sir I would be happy to work in this project please give me your Skype or email so that I can contact you directly

$1250 USD in 20 dage
(90 bedømmelser)

Hi, I have a huge experience with programmable logic devices (FPGAs, CPLDs). I can design a board with other Lattice CPLD (or other vendor: Xilinx, Altera, Microsemi, etc) - but will need some more informatinon abou Flere

$1250 USD in 20 dage
(13 bedømmelser)

A proposal has not yet been provided

$1250 USD in 20 dage
(3 bedømmelser)

Hi Mate, I JUST SEEN ATTACH DOCUMENT.. I have seen your project post and surely telling you that we have an experience for this kind of project development. We are best in outsourcing business since 2004 and we Flere

$1250 USD in 20 dage
(0 bedømmelser)

Hi I am having 10+ years of Experience in FPGA Design , I have worked on few re-engineered project , or you can say that from old FPGA to new FPGA, I can suggest following approach. 1) Convert jed into gate leve Flere

$1444 USD in 20 dage
(0 bedømmelser)

i am eager to work on this project. This will help to boost up my skills. It will also help to enhance my experience.

$1250 USD in 20 dage
(0 bedømmelser)

Hello, I am an embedded systems designer and developer and would love to work on this reverse engineering project as have ample experience. Since only jedec file will not be enough, I will need you to send me any Flere

$2222 USD in 20 dage
(0 bedømmelser)

Dear Project Manager, Although there is no way to regenerate source files from the programming file, it is still possible to reverse engineer the CPLD design. I finished a FPGA design for a client about 6 months ago Flere

$1666 USD in 20 dage
(0 bedømmelser)