Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit
I have 8 yrs of experience in verilog /VHDL . Designed many processors with pipeline without pipeline as well. I can do this very well without any issues.
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