Use the existing MIG controller and implement (simulation only) DDR2 and SRAM for xilinx virtex 5 fpga device. You just need to modify the MIG controller so that I can simulate the writing and reading as per my requirement.
My requirement is load an image of size 640x480 into DDR2 and read all the image contents. I would like to have the simulation perfectly with delay it takes to read from one row to another row within the same bank. If i switch to another bank and a different row and column, how much is the delay and etc.
Attached is the document which contains the information on how to download MIG controller and how to use the MIG controller. Xilinx also provides example design and user design vhdl files. You just need to use the design to work for my requirements.
6 freelancere byder i gennemsnit $293 på dette job
Hi I have 2+ years experience in memory interfaces ( DDR, SDRAM, PCM etc with spartan6 and virtex5 FPGAs). I will deliver the project with desired results. Thanks.
We are Xilinx specialist, + 15 years outsourcing FPGA consultancy We reserve the right of withdraw this proposal until agree a project specification. Walter D. Gallegos Programmable Logic & Software