I need an TCI/IP core implemented in Altera.
There should be a minimum Latency in all the modules implemented.
PHY chip: LXT972A from Intel.
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Hi I am having 10+ years of experience in FPGA/VHDL/Verilog. I am able to develop TCP/IP core inside FPGA which will interact with your Phy chip. Thanks Shobhit Kapoor