hello, I have this project where I need to read from files and print the output in one file.
I provided a very similar code , that can be modify and Matlab code to generate input files.
I am an experienced digital design engineer. I can help with your assignment on creating the read-write functions in vhdl. drop a line over chat if you have any questions. best regards,
4 freelancere byder i gennemsnit $76 på dette job
Hello, I am an electrical engineering master student at University of Alberta and did many projects with VHDL and VerilogHDL and I believe I can do this job perfectly.