Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS).

The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision.

The Reed Solomon En/Decoder must be set to (223,255)

The Interleaver must be parameterizable

A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock.

The Transmit Chain:

Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder-

The Receive Chain:

Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement

200 Mbps sustained decoding speed should me maintained.

Complete Simulation and HDL sources must be delivered.

The use of relevant Xilinx Evaluation cores are permitted.
All parameters should be set by registers.
It is a typical implementation of the standart TM SYNCHRONIZATION AND CHANNEL CODING which is located at https://public.ccsds.org/Pubs/131x0b2ec1s.pdf The relevant sections are: Section 3,4,5,8,9 which deal with the Viterbi decoder, RS encoder/decoder, framing and scrambling and it is much more restricted as we gave the specific parameters for the Viterbi and RS decoder. The implementation is sometimes referred as NASA CCSDS.
A simple noise generator (or AWGN) can be added just for test purposes, the Input output can be 4-8 bits.

Elektrisk Ingeniørarbejde Elektronik Microcontroller Telekommunikations Ingeniørarbejde Verilog / VHDL

Projekt ID: #16491276

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