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Analog Integrated Circuit Design (Cadence Virtuoso) NMOS switch

a) Derive an expression as a function of W/L for the “on-resistance” of an NMOS switch with the gate tied to V_DD . (Note: Neglect the body effect.) Use a V_DD = 1.8 V and V_t = 500 mV.

b) Using Cadence, sweep V_DS from -V_DD /2 to V_DD /2 and W/L with V_G = V_DD and V_S = V_DD/2. The body should be tied to V_SS and L = 500 nm. Show schematic and simulation results.

c) Repeat (a) - (b) using a PMOS. Use V_G = 0 V instead of V_DD and V_B = V DD . Assume |V_tp | = V_t .

d) Repeat (a) - (b) using an NMOS and PMOS in parallel. Size the PMOS k times larger where k is the ratio between parts (b) and (c). Use the correct V_G for each transistor.

If you do not have access to Cadence Virtuoso, we can do screen sharing and you can walk me through the steps

DEADLINE 12:00 P.M. PST

Evner: Elektrisk Ingeniørarbejde, Elektronik, Verilog / VHDL, Kredsløbs Design

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Om arbejdsgiveren:
( 21 bedømmelser ) San Diego, United States

Projekt ID: #21812039

3 freelancere byder i gennemsnit $110 på dette job

uxiaojuan2019

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Intel1994

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bibihawwa

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