Synthesis and Optimization of Digital Systems
Write a new TCL command to be integrated within Design Compiler that performs a timing-driven
Dual-Vth assignment. Main arguments of the command are:
-arrivalTime constraint actual timing constraint to match during optimization [ns]
-effortOpt low | high optimization effort; available options are high (max. leakage optimization)
and low (min execution time).
The command returns the list resList containing the following 4 items:
item 0--> power-savings: % of leakage reduction wrt the initial configuration;
item 1--> execution-time: difference between starting-time and end-time (seconds)*.
item 2--> lvt: % of LVT gates
item 3--> hvt: % of HVT gates
$resList$ dualVth_assignment [-effort low||high] –arrivalTime $constraint$
*Note: use the tcl clock command
Basic Rules for the Competition
1. Benchmarks: c1908.v c5315.v (clock-gating disabled).
2. The reference circuit is first synthesized using a single Low-Vt library (i.e., all LVT gates using the compile
command) under a fixed timing constraint (e.g., clockPeriod = 5.0 ns); the resulting netlist is then used
as starting point for the dualVth_assignement command.
3. The command will be executed under Design Compiler, just after dc_synthesis.tcl.
4. Only the numbers returned by the command through the resList will be considered for the competition.
· groups that will deliver the work in time will get 3 points;
· the algorithm that gets the highest power-savings with the minimum CPU time (for both options
effort low and high) will get 3 extra points;
· fake (or copied) scripts will get -3 points.