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Low-Power Optimization

Low-Power Contest

Synthesis and Optimization of Digital Systems

Write a new TCL command to be integrated within Design Compiler that performs a timing-driven

Dual-Vth assignment. Main arguments of the command are:

 -arrivalTime constraint  actual timing constraint to match during optimization [ns]

 -effortOpt low | high  optimization effort; available options are high (max. leakage optimization)

and low (min execution time).

The command returns the list resList containing the following 4 items:

item 0--> power-savings: % of leakage reduction wrt the initial configuration;

item 1--> execution-time: difference between starting-time and end-time (seconds)*.

item 2--> lvt: % of LVT gates

item 3--> hvt: % of HVT gates

SYNOPSIS

$resList$ dualVth_assignment [-effort low||high] –arrivalTime $constraint$

*Note: use the tcl clock command

Basic Rules for the Competition

1. Benchmarks: c1908.v c5315.v (clock-gating disabled).

2. The reference circuit is first synthesized using a single Low-Vt library (i.e., all LVT gates using the compile

command) under a fixed timing constraint (e.g., clockPeriod = 5.0 ns); the resulting netlist is then used

as starting point for the dualVth_assignement command.

3. The command will be executed under Design Compiler, just after dc_synthesis.tcl.

4. Only the numbers returned by the command through the resList will be considered for the competition.

5. Scores:

· groups that will deliver the work in time will get 3 points;

· the algorithm that gets the highest power-savings with the minimum CPU time (for both options

effort low and high) will get 3 extra points;

· fake (or copied) scripts will get -3 points.

Færdigheder: Digital Design, Elektrisk Ingeniørarbejde, Verilog / VHDL

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Om arbejdsgiveren:
( 0 bedømmelser ) Italy

Projekt-ID: #6037269

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tranchinh

Dear! I have three years experience in ASIC field, good command in RTL design and coding with Verilog. I've been working for Dolphin Technology Inc (at San Jose, CA) since I graduated. Currently I'm designing RTL for Mere

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crobert114

hello sir, I have three year experience on digital synthesis. please knock me when you are free. looking for hearing from you.

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QuiteOutstanding

I have quite outstanding knowledge about verilog because i completed a module in verilog another one has to be completed. I can systhesis, implement design and generate programming file in ISE project navigator. I can Mere

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