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Telemetry encoder on FPGA using VHDL language for Settalite - open to bidding

The project will comprise of three phases.

First phase will be the know how development of CCSDS Packet TM encoding Standard.

The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.

Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit

Færdigheder: Dataindførsel, Databehandling, Excel

Se mere: vhdl, vhdl fpga, open layers, fpga vhdl, encoding data entry, encoder data, data entry encoder, data encoding, project simulation using, data entry encoding, fpga development, excel encoding, fpga implementation, data entry data encoding, bidding kit, project using vhdl, simulation project using, simulation using, language fpga project, vhdl project bidding, vhdl implementation, vhdl fpga project, telemetry, project vhdl, fpga project bidding

Om arbejdsgiveren:
( 0 bedømmelser ) Philippines

Projekt-ID: #5996864

1 freelancer byder i gennemsnit $155 for dette job

princewhin

Dear Hiring Manager, I am interested in the job you recently posted. I am a graduate of Computer Science, and am very familiar with Data Entry, MS office and Web Researching. I am hardworking, disciplined and have Mere

$155 USD in 3 dage
(1 bedømmelse)
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