Tildelt

Matlab and Mathematica, Verilog / VHDL Job by pec24navin

hi,

I am studying in a college and i have to do a final year project which is already in Simulink and have to convert in VHDL. This VHDL code should be synthesised in a FPGA Development kit. Help me in this project, if you are interested send me a mail.

Regards,

Navin Ramalingam

Færdigheder: Matlab and Mathematica, Verilog / VHDL

Se mere: year 2013, vhdl fpga, navin, fpga vhdl, final year project, send final project, simulink project, fpga code, project final year, custom project jan 2013, fpga development, code college project, year project, vhdl fpga project, vhdl convert project, project vhdl, simulink fpga, project fpga code, final project college, code simulink, project fpga, fpga project, simulink convert code, convert simulink code, convert code simulink

Om arbejdsgiveren:
( 1 bedømmelse ) Warstein, Germany

Projekt-ID: #4111702

1 freelancer byder i gennemsnit $15 for dette job

MikroStar

Hired by the Employer

$15 USD / time
(45 bedømmelser)
6.6