Hardware Security - Module
Design , verify and validated RTL for securing a memory of 128KB.
Perform code coverage and synthesis of design as well.
Clock rate of design should be over 100 Mhz.
1. Synthesizable RTL code
2. Verification script (i.e. Automated Testbench)
3. Synthesis script
4. Code Coverage Report (>90% overall coverage)
5. Detailed drawings of FSM, block diagrams and verification diagrams used in project.
13 freelancere byder i gennemsnit $290 for dette job
Hi very good morning...! i am professor in engineering college, teaching and working on verilog. kindly brief about your project .Let chat and share more info. Waiting for your response thanks