In this project I need to optimize the code for Groestl miner VCU 1525 to smaller FPGA (Artix-7 XC7A200T). Groestl will be slightly modified and this modification will need to be reflected here. The optimal target speed is 50-70 MHs. (code [login to view URL])
You'll need to adjust the mining program for control and run on Linux (Raspberry Board).
I also want to switch the miner to another PHI 1612 algorithm.